Displaying 7 results from an estimated 7 matches for "esenciasetflag".
2016 Feb 19
3
Failure to match a DAG after a minor pattern change in a custom Target
...tanding of DAG patterns is quite weak, I'd appreciate any
help on this. For that matter, any opportunity to learn about LLVM is
welcomed. Original code, modified code as well as the error are provided
below. I can provide more if needed. There were two changes made. One in
the definition of SDT_EsenciaSetFlag and another in SF_RI class
(specifically in its DAG pattern).
Any help is appreciated.
========================= Orignal Code =====================================
def SDT_EsenciaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Esenciasetflag : SDNode<"Esenc...
2016 Feb 22
2
Failure to match a DAG after a minor pattern change in a custom Target
On Fri, Feb 19, 2016 at 6:10 AM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 2/18/2016 6:01 PM, Rail Shafigulin via llvm-dev wrote:
>
>> [(set SR:$rD, (Esenciasetflag (i32 GPR:$rA), (i32
>> immSExt16:$imm), (i32 Cond)))]> {
>>
>
> I suspect that the "set SR:$rD" is the problem here. The Esenciasetflag
> does not have any values that can be assigned to a
> register, so it's probably this part that causes the pattern to fa...
2016 Feb 26
0
Failure to match a DAG after a minor pattern change in a custom Target
On 2/22/2016 1:50 PM, Rail Shafigulin wrote:
> Would you mind showing how to make Esenciasetflag to actually set a
> flag? I can't figure out the syntax.
Is the "setflag" instruction setting something in a special register
(such as EFLAGS on x86)? If so, then you can add "let Defs [xyz] in
..." to your .td definition of that instruction and leave the "set&qu...
2016 Feb 05
3
New register class and patterns
...Allocatable = 0;
}
Then I changed an instruction class to return an explicit value
class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> :
InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
!strconcat(asmstr, "\t$rA, $rB"),
[(set SPR:$rC, (Esenciasetflag (i32 GPR:$rA), (i32
GPR:$rB), Cond))]> {
bits<5> op2;
bits<5> rA;
bits<5> rB;
let Inst{25-21} = op2;
let Inst{20-16} = rA;
let Inst{15-11} = rB;
let op2 = op2Val;
}
Naturally LLVM didn't like it. I'm getting stack dumps when I compile it.
I'm assumi...
2016 Feb 04
2
New register class and patterns
It does have an output register, it's just an implicit flag register. It
still has a DAG output. I'm not sure if the allocatable bit matters at this
point for selection purposes, but it does later. Not adding a type to the
register class can also be problematic (e.g. a flag register should have i1
added to regTypes for its class).
-Matt
>
Does LLVM make an assumption that there is an
2016 Feb 04
2
New register class and patterns
...eating a new register class would
cause a problem? In other words, since there is no output register, why
would LLVM start complaining. Below I'm repeating some code for reference.
Any help is appreciated.
def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Esenciasetflag : SDNode<"EsenciaISD::SET_FLAG", SDT_EsenciaSetFlag,
[SDNPOutGlue]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),...
2016 Feb 03
2
New register class and patterns
On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>
> On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote:
>
> def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
>
>
> I think for setting an implicit register, you still need to have 1 result
> here.
>
> If you look at