Displaying 6 results from an estimated 6 matches for "escalaisd".
2016 Feb 02
2
New register class and patterns
...register class in the pattern. i32:$sA should work etc.
>
> -Matt
>
> Let me clarify.
>
> I'm not sure I understand what you are saying. Let me post more information.
>
> Here is what I have defined for Escalasetflag
>
> def Escalasetflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,
> [SDNPOutGlue]>;
>
> How come it was working before and is is not working now? Clearly I'm missing something, but I can't figure out what.
>
> Any help is appreciated.
>
>
> --
> Rail Shafig...
2016 Jan 29
3
New register class and patterns
On Fri, Jan 29, 2016 at 10:22 AM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 1/28/2016 8:11 PM, Rail Shafigulin via llvm-dev wrote:
>
>>
>> Would anyone be able to figure out why this is happening? I can provide
>> more code if needed.
>>
>
> The error message should show what types have been inferred so far.
>
> You
2016 Feb 03
2
New register class and patterns
...lin <rail at esenciatech.com>
wrote:
>
> Let me clarify.
>>
>> I'm not sure I understand what you are saying. Let me post more
>> information.
>>
>> Here is what I have defined for Escalasetflag
>>
>> def Escalasetflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,
>> [SDNPOutGlue]>;
>>
>> How come it was working before and is is not working now? Clearly I'm
>> missing something, but I can't figure out what.
>>
>> Any help is appreciated.
>>
&...
2016 Jan 30
1
New register class and patterns
> On Jan 29, 2016, at 13:25, Rail Shafigulin via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
>
>
> I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details:
>
> defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
>
> multiclass SF<bits<5> op2Val, string asmstr, PatLeaf
2016 Feb 04
2
New register class and patterns
...alasetflag (i32 GPR:$rA), immSExt16:$imm, Cond), I
can't find anything saying that it sets a flag in the special purpose
register.
I'm reposting code for convenience.
def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
def Escalatflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag,
[SDNPOutGlue]>;
def Escala_CC_EQ : PatLeaf<(imm),
[{return (N->getZExtValue() == ISD::SETEQ);}]>;
class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond>
: InstRI<0xf, (outs), (ins GP...
2016 Feb 04
2
New register class and patterns
>
>
>
>
> def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
> SDTCisVec<1>,
> SDTCisSameAs<2, 1>]>;
>
> This is confusing to me. This tells me that there is 1 result but and 2
> operands. But then it says that operands 2 and 1 are of the same type,