search for: entrytoken

...he above code that say: LLVM ERROR: Cannot yet select: 0x170f200: ch = br_cc 0x170f000, 0x170ed00, 0x170dc60, 0x170ec00, 0x170ef00 [ID=19] 0x170f000: ch = TokenFactor 0x170e560, 0x170e760, 0x170e960 [ID=18] 0x170e560: ch = CopyToReg 0x16d5748, 0x170e460, 0x170df60 [ID=15] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170e460: i16 = Register %reg16384 [ID=5] 0x170df60: i16,ch = CopyFromReg 0x16d5748, 0x170de60 [ID=12] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170de60: i16 = Register %reg16388 [ID=2] 0x170e760: ch = CopyToReg 0x16d5748, 0x170e660, 0x170e160 [ID=16]...

...88c94d8, 0x88c9118 Replacing.3 0x88c8a20: i1 = setcc 0x88c9180, 0x88c94d8, 0x88c9118 With: 0x88c89a8: i1 = setcc 0x88c8fc8, 0x88c9060, 0x88c9360 Lowered selection DAG: SelectionDAG has 16 nodes: 0x88c8c00: i32 = Constant <0> 0x88c8c68: i32 = Constant <536870912> 0x88c88a0: ch = EntryToken 0x88c8c00: <multiple use> 0x88c8c00: <multiple use> 0x88c8c68: <multiple use> 0x88c8c68: <multiple use> 0x88c8d18: i32,i32,ch = formal_arguments 0x88c88a0, 0x88c8c00, 0x88c8c00, 0x88c8c68, 0x88c8c68 0x88c8d70: i32 = FrameIndex <0> 0x88c8dd8: i32...

...[0] 0x213b8f0: f64,ch = load 0x213b780, 0x213aa90, 0x213b610 <0x2113690:0> alignment=8 [0] 0x213b780: ch = Prefetch 0x213aee0:1, 0x213b1c0, 0x213b330, 0x213b4a0 [1] 0x213aee0: f64,ch = load 0x213a720, 0x213ac00, 0x213b610 <0x215ace8:0> alignment=8 [0] 0x213a720: ch = EntryToken [0] 0x213ac00: i64,ch = CopyFromReg 0x213a720, 0x213ad70 [0] 0x213a720: ch = EntryToken [0] 0x213ad70: i64 = Register #1024 [0] 0x213b610: i64 = undef [0] 0x213b1c0: i64 = add 0x213ac00, 0x213b050 [0] 0x213ac00: i64,ch = CopyFromReg 0x213a720, 0...

...nfrastructure and now trying to extend Z80InstrInfo.td to handle more and more C code. > I have done some work with FrameIndex and now I am stuck with assert. > > llc: SelectionDAG.cpp:645: bool llvm::SelectionDAG::RemoveNodeFromCSEMaps(llvm::SDNode*): Assertion `N->getOpcode() != ISD::EntryToken && "EntryToken in CSEMap!"' failed. > > This code works: > > void simple() > { > unsigned char i=10; > unsigned char a = 20; > } > > and produces my somewhat not VERY REAL z80 assembly: > > .file "simple.bc" > .text > .gl...

Have you read http://llvm.org/docs/WritingAnLLVMBackend.html and http://llvm.org/docs/CodeGenerator.html ? http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector describes how to define a store instruction. -Eli On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote: > Please correct me i m stuck at this point. > > On Jul 6, 2017 5:18 PM, "hameeza ahmed"

...equested for this function ---- Branch Probability Info : foo ---- Computing probabilities for scalar.ph Computing probabilities for vector.body Computing probabilities for min.iters.checked === foo Initial selection DAG: BB#0 'foo:min.iters.checked' SelectionDAG has 1 nodes: t0: ch = EntryToken Combining: t0: ch = EntryToken Optimized lowered selection DAG: BB#0 'foo:min.iters.checked' SelectionDAG has 1 nodes: t0: ch = EntryToken Legally typed node: t0: ch = EntryToken Legally typed node: t65535: ch = handlenode t0 Type-legalized selection DAG: BB#0 'foo:min.iters.ch...

...g probabilities for if.then Computing probabilities for if.else Computing probabilities for entry set edge entry -> 1 successor weight to 20 set edge entry -> 0 successor weight to 12 === isZero Initial selection DAG: BB#0 'isZero:entry' SelectionDAG has 16 nodes: 0x17d0fb0: ch = EntryToken [ORD=1] 0x17f6880: i32 = FrameIndex<1> [ORD=1] 0x17f6a80: i32 = undef [ORD=1] 0x17d0fb0: <multiple use> 0x17d0fb0: <multiple use> 0x17f6680: i32 = Register %vreg0 [ORD=1] 0x17f6780: i32,ch = CopyFromReg 0x17d0fb0, 0x17f6680 [ORD=1] 0x17f6880: <m...

...that I never defined any separate floating point registers, not sure if this will pose any issue? Thanks again for your time! Jeff jeff at ubuntu:~/code$ llc -debug-only=isel dft_gf_msp.ll === main Initial selection DAG: BB#0 'main:entry' SelectionDAG has 18 nodes: t0: ch = EntryToken t4: ch = store<ST4[%retval]> t0, Constant:i32<0>, FrameIndex:i32<0>, undef:i32 t7: ch = store<ST4[%sz]> t4, Constant:i32<256>, FrameIndex:i32<2>, undef:i32 t10: ch = store<ST4[%dir]> t7, ConstantFP:f32<-1.000000e+00>, FrameInde...

...romoted by the Legalization Pass?! I attached the shortened isel-dump, so if anyone could have a short look on that I would be very thankful! Jan -------------- next part -------------- Initial selection DAG: BB#11 '_main:for.cond164.preheader' SelectionDAG has 17 nodes: 0x1f34090: ch = EntryToken [ORD=161] 0x1f34090: <multiple use> 0x1f8d210: i32 = FrameIndex<2> [ORD=158] 0x1f63860: i32 = Constant<32> [ORD=159] 0x1f8ce10: i32 = add 0x1f8d210, 0x1f63860 [ORD=159] 0x1f60d60: i32 = undef [ORD=161] 0x1f5f040: i32,ch = load 0x1f34090, 0x1f8ce10, 0...

...rely on library calls for certain operations (like sdiv). We recently ran into a problem where these operations that are expanded to library calls aren't maintaining the proper ordering in relation to other chains in the DAG. The following snippet of a DAG demonstrates the problem. t0: ch = EntryToken t2: i64,ch,glue = CopyFromReg t0, Register:i64 %reg0 t4: i64,ch,glue = CopyFromReg t2:1, Register:i64 %reg1, t2:1 t6: i64,ch,glue = CopyFromReg t4:1, Register:i64 %reg2, t4:1 t8: i64,ch,glue = CopyFromReg t6:1, Register:i64 %reg3, t6:1 t11: ch = CopyToReg t0, Register:i64 %vreg0, t2...

Hi, I am having some issues with how some of the instructions are being legalized. So this is my intial basic block. The area of concern is the last three instructions. I will pick and choose debug output to keep this small. SelectionDAG has 36 nodes: t0: ch = EntryToken t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 t4: i32 = or t2, Constant:i32<256> t9: i32 = shl t4, Constant:i32<2> t10: i32 = add t6, t9 t12: i32,ch = CopyFromReg t0, Reg...

...ome issues with how some of the instructions are being >> legalized. >> So this is my intial basic block. The area of concern is the last three >> instructions. I will pick and choose debug output to keep this small. >> >> SelectionDAG has 36 nodes: >> t0: ch = EntryToken >> t6: i32,ch = CopyFromReg t0, Register:i32 %vreg507 >> t2: i32,ch = CopyFromReg t0, Register:i32 %vreg17 >> t4: i32 = or t2, Constant:i32<256> >> t9: i32 = shl t4, Constant:i32<2> >> t10: i32 = add t6,...

Is there any way to get it to delay this optimization where it goes from this: Initial selection DAG: BB#0 'bclr64:entry' SelectionDAG has 14 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 t6: i64 = sub t4, Constant:i64<1> t7: i64 = shl Constant:i64<1>, t6 t9: i64 = xor t7, Constant:i64<-1> t10: i64 = and t2, t9 t12: ch,gl...

...6 at 2:07 PM, Phil Tomson <phil.a.tomson at gmail.com> > wrote: > >> Is there any way to get it to delay this optimization where it goes from >> this: >> >> Initial selection DAG: BB#0 'bclr64:entry' >> SelectionDAG has 14 nodes: >> t0: ch = EntryToken >> t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 >> t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 >> t6: i64 = sub t4, Constant:i64<1> >> t7: i64 = shl Constant:i64<1>, t6 >> t9: i64 = xor t7, Constant:i64<...

I have the following selection DAG: SelectionDAG has 9 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t16: i32,ch = load<LD1[%ptr](tbaa=<0x10023c9f448>), anyext from i8> t0, t2, undef:i64 t15: v16i8 = BUILD_VECTOR t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16, t16 t11: ch,glue = CopyToReg t0, Regist...

...r1, r0, r1, 64 %sub = sub i64 %b, 1 %shl = shl i64 1, %sub %xor = xor i64 %shl, -1 %and = and i64 %a, %xor ret i64 %and } I ran llc with -debug to get a better idea of what's going on and found: Initial selection DAG: BB#0 'bclr64:entry' SelectionDAG has 14 nodes: t0: ch = EntryToken t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 t6: i64 = sub t4, Constant:i64<1> t7: i64 = shl Constant:i64<1>, t6 t9: i64 = xor t7, Constant:i64<-1> t10: i64 = and t2, t9 t12: ch,gl...

...@boolvar = internal global i1 false define void @set_boolvar() nounwind { entry: store i1 true, i1* @boolvar, align 16 ret void } This gets legalized to: === set_boolvar Initial selection DAG: SelectionDAG has 7 nodes: 0xe00711c: i32 = Constant <0> 0xcc056f0: ch = EntryToken 0xe00700c: i1 = Constant <-1> 0xe007094: i32 = GlobalAddress <i1* @boolvar> 0 0xe0071a4: i32 = undef 0xe00722c: ch = store 0xcc056f0, 0xe00700c, 0xe007094, 0xe0071a4 <0xcc02bbc:0> alignment=16 0xe0072b4: ch = ret 0xe00722c Optimized lowered selection DAG:...

Hi, I am having issues running a new backend that I created for a new architecture. I suspect these errors may have something to do with how I have the string setup in LLVMTargetMachine() below? Also - It would be great if someone could point me to a document that describes some of these error messages? For example what does t26 ..t4 mean? Thanks in advance for taking your valuable time to help

...a.tomson at gmail.com>> wrote: > > Is there any way to get it to delay this optimization where > it goes from this: > > Initial selection DAG: BB#0 'bclr64:entry' > SelectionDAG has 14 nodes: > t0: ch = EntryToken > t2: i64,ch = CopyFromReg t0, Register:i64 %vreg0 > t4: i64,ch = CopyFromReg t0, Register:i64 %vreg1 > t6: i64 = sub t4, Constant:i64<1> > t7: i64 = shl Constant:i64<1>, t6 >...

Here is a last example to illustrate my concern. The problem is about the lowering of node t13. Initial selection DAG: BB#0 '_start:entry' SelectionDAG has 44 nodes: t11: i16 = Constant<0> t0: ch = EntryToken t3: ch = llvm.clp.set.rspa t0, TargetConstant:i16<392>, Constant:i32<64> t5: ch = llvm.clp.set.rspb t3, TargetConstant:i16<393>, Constant:i32<64> t8: ch = llvm.clp.set.rspsu t5, TargetConstant:i16<394>, Constant:i32<8>...