search for: decodernamespaces

...decoding table by setting the DecoderNamespace. This way in XCoreDisassembler::getInstruction() I can call decodeInstruction() on the first decoder table (containing INITSP_2r) and if this fails I can then call decodeInstruction() on the second decoder table (containing ADD_3r). Is this an abuse of DecoderNamespaces? Is there a better way of solving my problem? Thanks, Richard

I'm trying to implement the standalone assembler for mips and I have encountered a problem in instruction operands matcher. In mips instruction set there are math instructions with two format flags in the mnemonic, one for source and one for destination register. For example ceil.w.s means both source and destination are F32 registers while ceil.l.d means both source and destination are F64

...decoding table by setting the DecoderNamespace. This way in XCoreDisassembler::getInstruction() I can call decodeInstruction() on the first decoder table (containing INITSP_2r) and if this fails I can then call decodeInstruction() on the second decoder table (containing ADD_3r). Is this an abuse of DecoderNamespaces? Is there a better way of solving my problem? > > Thanks, > > Richard > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

On May 22, 2012, at 8:05 AM, "Medic, Vladimir" <vmedic at mips.com> wrote: > I'm trying to implement the standalone assembler for mips and I have encountered a problem in instruction operands matcher. > In mips instruction set there are math instructions with two format flags in the mnemonic, one for source and one for destination register. > For example ceil.w.s

Hi All, I have faced decoding conflict of DisassemblerTables from TableGen. I have instructions with same encoding and different mnemonic among different architecture versions. I have used Predicates and AssemblerPredicates to distinguish them on Codegen and Assembler but it does not work on Disassembler. When I look at TableGen/FixedLenDecoderEmitter.cpp, once there is decoding conflict,

Hi all, Short version I get decoding conflicts during generation of disassembler tables for my modified PowerPC backend: 001100.......................... ................................ ADDIC 001100__________________________ E_LBZ 001100__________________________ Which methods can be used to resolve this kind of error? Long version: I'm trying to implement support for the PowerPC

Hi, I'm not sure how to handle some of the trickier instruction encodings in MIPS64r6. My problem is that some instructions determine the operation based on the relationship between two fields. For example, 'beqc $rs, $rt, offset' (branch if equal, no delay slot) and bovc (branch if addition would overflow, no delay slot) share the same major opcode and field layout. When the register

I've been working on adding support for a (semi-proprietary) extension for PowerPC called "Paired-Singles". It's a SIMD instruction set supporting various operations on a vector of 2 32-bit floating point numbers. The Extension is found in the PowerPC 750CL, modified variants of it are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and the Nintendo Wii U

def STOREbos { // InstructionEncoding Instruction RPPInst RPPInstMMEMrr &nbsp; field bits<32&gt; Inst = { 0, 0, 0, 1, rs1{2}, rs1{1}, rs1{0}, index{0}, 0, 0, 0, 1, 0, rbase{3}, rbase{2}, rbase{1}, rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; &nbsp; field bits<32&gt; SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

You are welcome. I changed the pattern, the same old error pop up again, crash in the same place. Type set is empty for each HW mode: possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records). vtInt: &nbsp; (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824!

Hi Krzysztof, Today I try it on llvm9.0.0 version. &nbsp; def bos : RPPInstMMEMrr<OPC_STORE, &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; (outs), (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift), &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; !strconcat(opcodestr, ""), "$rs1,