Charlotte Delenk via llvm-dev
2020-Aug-25 10:00 UTC
[llvm-dev] [TableGen] What to do if there are overlapping instruction patterns?
I've been working on adding support for a (semi-proprietary) extension for PowerPC called "Paired-Singles". It's a SIMD instruction set supporting various operations on a vector of 2 32-bit floating point numbers. The Extension is found in the PowerPC 750CL, modified variants of it are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and the Nintendo Wii U (Espresso) It's been going pretty well so far, however the biggest hurdle I have encountered was that the testsuite is failing because the instruction space for Paired Singles has been reused for ISA 3.1 and VMX. Is there a way to disembiguate them further? You can see my current patch at https://reviews.llvm.org/D85137 and it already prevents you from enabling Altivec and Paired Singles at the same time.
Charlotte Delenk via llvm-dev
2020-Aug-25 10:19 UTC
[llvm-dev] [TableGen] What to do if there are overlapping instruction patterns?
On 8/25/20 11:00 AM, Charlotte Delenk via llvm-dev wrote:> I've been working on adding support for a (semi-proprietary) extension > for PowerPC called "Paired-Singles". It's a SIMD instruction set > supporting various operations on a vector of 2 32-bit floating point > numbers. > > The Extension is found in the PowerPC 750CL, modified variants of it > are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) > and the Nintendo Wii U (Espresso) > > It's been going pretty well so far, however the biggest hurdle I have > encountered was that the testsuite is failing because the instruction > space for Paired Singles has been reused for ISA 3.1 and VMX. > > Is there a way to disembiguate them further? You can see my current > patch at https://reviews.llvm.org/D85137 and it already prevents you > from enabling Altivec and Paired Singles at the same time. > >I should have added the decoding conflicts output generated by the build step of PPCGenDisassemblerTables.inc in my previous email. Most worrisome is is the psq_st entry as that conflicts with over a hundred entries, however this is the immediate-offset store instruction for paired singles which makes it quite important -------------- next part -------------- Decoding Conflict: 000100...................0001100 000100....................001100 000100.......................... ................................ PSQ_LX 000100___________________0001100 VGBBD 000100_____00000_____10100001100 VMRGEW 000100_______________11110001100 VMRGHB 000100_______________00000001100 VMRGHW 000100_______________00010001100 VMRGLB 000100_______________00100001100 VMRGLW 000100_______________00110001100 VMRGOW 000100_______________11010001100 VSLO 000100_______________10000001100 VSPLTB 000100_______________01000001100 VSPLTISB 000100__________0000001100001100 VSPLTISW 000100__________0000001110001100 VSPLTW 000100_______________01010001100 Decoding Conflict: 000100....................010111 000100.......................... ................................ PS_SUM1_rec 000100____________________010111 VMSUMCUD 000100____________________010111 Decoding Conflict: 000100....................011100 000100.......................... ................................ PS_MADDS0 000100____________________011100 VEXTDUWVLX 000100____________________011100 Decoding Conflict: 000100....................011101 000100.......................... ................................ PS_MADDS0_rec 000100____________________011101 VEXTDUWVRX 000100____________________011101 Decoding Conflict: 000100....................011110 000100.......................... ................................ PS_MADDS1 000100____________________011110 VEXTDDVLX 000100____________________011110 Decoding Conflict: 000100....................011111 000100.......................... ................................ PS_MADDS1_rec 000100____________________011111 VEXTDDVRX 000100____________________011111 Decoding Conflict: 000100....................101110 000100.......................... ................................ PS_SEL 000100____________________101110 VMADDFP 000100____________________101110 Decoding Conflict: 000100....................101111 000100.......................... ................................ PS_SEL_rec 000100____________________101111 VNMSUBFP 000100____________________101111 Decoding Conflict: 000100.....00000.....00000110000 000100...............00000110000 000100....................110000 000100.......................... ................................ PS_RES 000100_____00000_____00000110000 PS_RSQRTE 000100_____00000_____00000110000 Decoding Conflict: 000100.....00000.....00000110001 000100...............00000110001 000100....................110001 000100.......................... ................................ PS_RES_rec 000100_____00000_____00000110001 PS_RSQRTE_rec 000100_____00000_____00000110001 Decoding Conflict: 000100....................111011 000100.......................... ................................ PS_MADD_rec 000100____________________111011 VPERMR 000100____________________111011 Decoding Conflict: 000100....................111100 000100.......................... ................................ PS_NMSUB 000100____________________111100 VADDEUQM 000100____________________111100 Decoding Conflict: 000100....................111101 000100.......................... ................................ PS_NMSUB_rec 000100____________________111101 VADDECUQ 000100____________________111101 Decoding Conflict: 000100....................111110 000100.......................... ................................ PS_NMADD 000100____________________111110 VSUBEUQM 000100____________________111110 Decoding Conflict: 000100....................111111 000100.......................... ................................ PS_NMADD_rec 000100____________________111111 VSUBECUQ 000100____________________111111 Decoding Conflict: 111100..._______................ 111100.......................... ................................ PSQ_ST 111100__________________________ XSABSDP 111100_____00000_____101011001__ XSADDDP 111100_______________00100000___ XSADDSP 111100_______________00000000___ XSCMPEQDP 111100_______________00000011___ XSCMPEXPDP 111100___00__________00111011__0 XSCMPGEDP 111100_______________00010011___ XSCMPGTDP 111100_______________00001011___ XSCMPODP 111100___00__________00101011__0 XSCMPUDP 111100___00__________00100011__0 XSCPSGNDP 111100_______________10110000___ XSCVDPHP 111100_____10001_____101011011__ XSCVDPSP 111100_____00000_____100001001__ XSCVDPSPN 111100_____00000_____100001011__ XSCVDPSXDS 111100_____00000_____101011000__ XSCVDPSXWS 111100_____00000_____001011000__ XSCVDPUXDS 111100_____00000_____101001000__ XSCVDPUXWS 111100_____00000_____001001000__ XSCVHPDP 111100_____10000_____101011011__ XSCVSPDP 111100_____00000_____101001001__ XSCVSPDPN 111100_____00000_____101001011__ XSCVSXDDP 111100_____00000_____101111000__ XSCVSXDSP 111100_____00000_____100111000__ XSCVUXDDP 111100_____00000_____101101000__ XSCVUXDSP 111100_____00000_____100101000__ XSDIVDP 111100_______________00111000___ XSDIVSP 111100_______________00011000___ XSIEXPDP 111100_______________1110010110_ XSMADDADP 111100_______________00100001___ XSMADDASP 111100_______________00000001___ XSMADDMDP 111100_______________00101001___ XSMADDMSP 111100_______________00001001___ XSMAXCDP 111100_______________10000000___ XSMAXDP 111100_______________10100000___ XSMAXJDP 111100_______________10010000___ XSMINCDP 111100_______________10001000___ XSMINDP 111100_______________10101000___ XSMINJDP 111100_______________10011000___ XSMSUBADP 111100_______________00110001___ XSMSUBASP 111100_______________00010001___ XSMSUBMDP 111100_______________00111001___ XSMSUBMSP 111100_______________00011001___ XSMULDP 111100_______________00110000___ XSMULSP 111100_______________00010000___ XSNABSDP 111100_____00000_____101101001__ XSNEGDP 111100_____00000_____101111001__ XSNMADDADP 111100_______________10100001___ XSNMADDASP 111100_______________10000001___ XSNMADDMDP 111100_______________10101001___ XSNMADDMSP 111100_______________10001001___ XSNMSUBADP 111100_______________10110001___ XSNMSUBASP 111100_______________10010001___ XSNMSUBMDP 111100_______________10111001___ XSNMSUBMSP 111100_______________10011001___ XSRDPI 111100_____00000_____001001001__ XSRDPIC 111100_____00000_____001101011__ XSRDPIM 111100_____00000_____001111001__ XSRDPIP 111100_____00000_____001101001__ XSRDPIZ 111100_____00000_____001011001__ XSREDP 111100_____00000_____001011010__ XSRESP 111100_____00000_____000011010__ XSRSP 111100_____00000_____100011001__ XSRSQRTEDP 111100_____00000_____001001010__ XSRSQRTESP 111100_____00000_____000001010__ XSSQRTDP 111100_____00000_____001001011__ XSSQRTSP 111100_____00000_____000001011__ XSSUBDP 111100_______________00101000___ XSSUBSP 111100_______________00001000___ XSTDIVDP 111100___00__________00111101__0 XSTSTDCDP 111100_______________101101010_0 XSTSTDCSP 111100_______________100101010_0 XSXEXPDP 111100_____00000_____101011011_0 XSXSIGDP 111100_____00001_____101011011_0 XVABSDP 111100_____00000_____111011001__ XVABSSP 111100_____00000_____110011001__ XVADDDP 111100_______________01100000___ XVADDSP 111100_______________01000000___ XVCMPEQDP 111100_______________01100011___ XVCMPEQDP_rec 111100_______________11100011___ XVCMPEQSP 111100_______________01000011___ XVCMPEQSP_rec 111100_______________11000011___ XVCMPGEDP 111100_______________01110011___ XVCMPGEDP_rec 111100_______________11110011___ XVCMPGESP 111100_______________01010011___ XVCMPGESP_rec 111100_______________11010011___ XVCMPGTDP 111100_______________01101011___ XVCMPGTDP_rec 111100_______________11101011___ XVCMPGTSP 111100_______________01001011___ XVCMPGTSP_rec 111100_______________11001011___ XVCPSGNDP 111100_______________11110000___ XVCPSGNSP 111100_______________11010000___ XVCVDPSP 111100_____00000_____110001001__ XVCVDPSXDS 111100_____00000_____111011000__ XVCVDPSXWS 111100_____00000_____011011000__ XVCVDPUXDS 111100_____00000_____111001000__ XVCVDPUXWS 111100_____00000_____011001000__ XVCVHPSP 111100_____11000_____111011011__ XVCVSPDP 111100_____00000_____111001001__ XVCVSPHP 111100_____11001_____111011011__ XVCVSPSXDS 111100_____00000_____110011000__ XVCVSPSXWS 111100_____00000_____010011000__ XVCVSPUXDS 111100_____00000_____110001000__ XVCVSPUXWS 111100_____00000_____010001000__ XVCVSXDDP 111100_____00000_____111111000__ XVCVSXDSP 111100_____00000_____110111000__ XVCVSXWDP 111100_____00000_____011111000__ XVCVSXWSP 111100_____00000_____010111000__ XVCVUXDDP 111100_____00000_____111101000__ XVCVUXDSP 111100_____00000_____110101000__ XVCVUXWDP 111100_____00000_____011101000__ XVCVUXWSP 111100_____00000_____010101000__ XVDIVDP 111100_______________01111000___ XVDIVSP 111100_______________01011000___ XVIEXPDP 111100_______________11111000___ XVIEXPSP 111100_______________11011000___ XVMADDADP 111100_______________01100001___ XVMADDASP 111100_______________01000001___ XVMADDMDP 111100_______________01101001___ XVMADDMSP 111100_______________01001001___ XVMAXDP 111100_______________11100000___ XVMAXSP 111100_______________11000000___ XVMINDP 111100_______________11101000___ XVMINSP 111100_______________11001000___ XVMSUBADP 111100_______________01110001___ XVMSUBASP 111100_______________01010001___ XVMSUBMDP 111100_______________01111001___ XVMSUBMSP 111100_______________01011001___ XVMULDP 111100_______________01110000___ XVMULSP 111100_______________01010000___ XVNABSDP 111100_____00000_____111101001__ XVNABSSP 111100_____00000_____110101001__ XVNEGDP 111100_____00000_____111111001__ XVNEGSP 111100_____00000_____110111001__ XVNMADDADP 111100_______________11100001___ XVNMADDASP 111100_______________11000001___ XVNMADDMDP 111100_______________11101001___ XVNMADDMSP 111100_______________11001001___ XVNMSUBADP 111100_______________11110001___ XVNMSUBASP 111100_______________11010001___ XVNMSUBMDP 111100_______________11111001___ XVNMSUBMSP 111100_______________11011001___ XVRDPI 111100_____00000_____011001001__ XVRDPIC 111100_____00000_____011101011__ XVRDPIM 111100_____00000_____011111001__ XVRDPIP 111100_____00000_____011101001__ XVRDPIZ 111100_____00000_____011011001__ XVREDP 111100_____00000_____011011010__ XVRESP 111100_____00000_____010011010__ XVRSPI 111100_____00000_____010001001__ XVRSPIC 111100_____00000_____010101011__ XVRSPIM 111100_____00000_____010111001__ XVRSPIP 111100_____00000_____010101001__ XVRSPIZ 111100_____00000_____010011001__ XVRSQRTEDP 111100_____00000_____011001010__ XVRSQRTESP 111100_____00000_____010001010__ XVSQRTDP 111100_____00000_____011001011__ XVSQRTSP 111100_____00000_____010001011__ XVSUBDP 111100_______________01101000___ XVSUBSP 111100_______________01001000___ XVTDIVDP 111100___00__________01111101__0 XVTDIVSP 111100___00__________01011101__0 XVTSTDCDP 111100_______________1111_101___ XVTSTDCSP 111100_______________1101_101___ XVXEXPDP 111100_____00000_____111011011__ XVXEXPSP 111100_____01000_____111011011__ XVXSIGDP 111100_____00001_____111011011__ XVXSIGSP 111100_____01001_____111011011__ XXBRD 111100_____10111_____111011011__ XXBRH 111100_____00111_____111011011__ XXBRQ 111100_____11111_____111011011__ XXBRW 111100_____01111_____111011011__ XXEXTRACTUW 111100_______________010100101__ XXGENPCVBM 111100_______________1110010100_ XXGENPCVDM 111100_______________1110110101_ XXGENPCVHM 111100_______________1110010101_ XXGENPCVWM 111100_______________1110110100_ XXINSERTW 111100_______________010110101__ XXLAND 111100_______________10000010___ XXLANDC 111100_______________10001010___ XXLEQV 111100_______________10111010___ XXLNAND 111100_______________10110010___ XXLNOR 111100_______________10100010___ XXLOR 111100_______________10010010___ XXLORC 111100_______________10101010___ XXLXOR 111100_______________10011010___ XXMRGHW 111100_______________00010010___ XXMRGLW 111100_______________00110010___ XXPERM 111100_______________00011010___ XXPERMDI 111100_______________0__01010___ XXPERMR 111100_______________00111010___ XXSEL 111100____________________11____ XXSLDWI 111100_______________0__00010___ XXSPLTIB 111100_____00________0101101000_ XXSPLTW 111100_____000_______010100100__
Hal Finkel via llvm-dev
2020-Aug-25 11:51 UTC
[llvm-dev] [TableGen] What to do if there are overlapping instruction patterns?
Hi, Charlotte,
You can set a different decoding namespace for the new instructions. We
have this for SPE instructions, and this is what we did for QPX
instructions when those were supported.
In TableGen, you surround the instructions with something like:
let DecoderNamespace = "PairedSingles" in {
and then in Disassembler/PPCDisassembler.cpp, you'll have something like:
if (STI.getFeatureBits()[PPC::FeaturePairedSingles]) {
DecodeStatus result decodeInstruction(DecoderTablePairedSingles32,
MI, Inst, Address,
this, STI);
if (result != MCDisassembler::Fail)
return result;
} else if (STI.getFeatureBits()[PPC::FeatureSPE]) {
-Hal
On 8/25/20 5:00 AM, Charlotte Delenk via llvm-dev wrote:> I've been working on adding support for a (semi-proprietary) extension
> for PowerPC called "Paired-Singles". It's a SIMD instruction
set
> supporting various operations on a vector of 2 32-bit floating point
> numbers.
>
> The Extension is found in the PowerPC 750CL, modified variants of it
> are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway)
> and the Nintendo Wii U (Espresso)
>
> It's been going pretty well so far, however the biggest hurdle I have
> encountered was that the testsuite is failing because the instruction
> space for Paired Singles has been reused for ISA 3.1 and VMX.
>
> Is there a way to disembiguate them further? You can see my current
> patch at https://reviews.llvm.org/D85137 and it already prevents you
> from enabling Altivec and Paired Singles at the same time.
>
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory
Charlotte Delenk via llvm-dev
2020-Aug-25 14:50 UTC
[llvm-dev] [TableGen] What to do if there are overlapping instruction patterns?
On 8/25/20 12:51 PM, Hal Finkel wrote:> Hi, Charlotte, > > You can set a different decoding namespace for the new instructions. > We have this for SPE instructions, and this is what we did for QPX > instructions when those were supported.Hi Hal, Didn't know about that, it seems to work. thank you for your quick response.