search for: decodernamespace

...on testing to see if it can be decoded as an ADD_3r instruction but instead it stops looking at this point and returns Fail. How should I deal with this situation? One idea I had (which I haven't tried yet) is to move the troublesome instructions into a different decoding table by setting the DecoderNamespace. This way in XCoreDisassembler::getInstruction() I can call decodeInstruction() on the first decoder table (containing INITSP_2r) and if this fails I can then call decodeInstruction() on the second decoder table (containing ADD_3r). Is this an abuse of DecoderNamespaces? Is there a better way of so...

...ters. Also, depending on the floating point unit configuration F64 may be either single 64 bit register or a pair of 32 bit registers. In the current implementation this instruction is defined as follows: // Instructions that convert an FP value to 64-bit fixed point. let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in multiclass FFR1_L_M<bits<6> funct, string opstr> { def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>; def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>; } // Instructions that convert an FP value to 32-bit fixed poin...

...g to see if it can be decoded as an ADD_3r instruction but instead it stops looking at this point and returns Fail. > > How should I deal with this situation? One idea I had (which I haven't tried yet) is to move the troublesome instructions into a different decoding table by setting the DecoderNamespace. This way in XCoreDisassembler::getInstruction() I can call decodeInstruction() on the first decoder table (containing INITSP_2r) and if this fails I can then call decodeInstruction() on the second decoder table (containing ADD_3r). Is this an abuse of DecoderNamespaces? Is there a better way of so...

...ending on the floating point unit configuration F64 may be either single 64 bit register or a pair of 32 bit registers. In the current implementation this instruction is defined as follows: > > // Instructions that convert an FP value to 64-bit fixed point. > let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in > multiclass FFR1_L_M<bits<6> funct, string opstr> { > def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>; > def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>; > } > > // Instructions that convert an...

Hi All, I have faced decoding conflict of DisassemblerTables from TableGen. I have instructions with same encoding and different mnemonic among different architecture versions. I have used Predicates and AssemblerPredicates to distinguish them on Codegen and Assembler but it does not work on Disassembler. When I look at TableGen/FixedLenDecoderEmitter.cpp, once there is decoding conflict,

Hi all, Short version I get decoding conflicts during generation of disassembler tables for my modified PowerPC backend: 001100.......................... ................................ ADDIC 001100__________________________ E_LBZ 001100__________________________ Which methods can be used to resolve this kind of error? Long version: I'm trying to implement support for the PowerPC

Hi, I'm not sure how to handle some of the trickier instruction encodings in MIPS64r6. My problem is that some instructions determine the operation based on the relationship between two fields. For example, 'beqc $rs, $rt, offset' (branch if equal, no delay slot) and bovc (branch if addition would overflow, no delay slot) share the same major opcode and field layout. When the register

I've been working on adding support for a (semi-proprietary) extension for PowerPC called "Paired-Singles". It's a SIMD instruction set supporting various operations on a vector of 2 32-bit floating point numbers. The Extension is found in the PowerPC 750CL, modified variants of it are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and the Nintendo Wii U

...rbase{0}, rbase{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; &nbsp; field bits<32&gt; SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; &nbsp; int Size = 4; &nbsp; string DecoderNamespace = ""; &nbsp; list<Predicate&gt; Predicates = []; &nbsp; string DecoderMethod = ""; &nbsp; bit hasCompleteDecoder = 1; &nbsp; string Namespace = "RPP"; &nbsp; dag OutOperandList = (outs); &nbsp; dag InOperandList = (ins MGPR:$rs1, SGPR32:$...

...e{4}, roffset{4}, roffset{3}, roffset{2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; &nbsp; field bits<32&gt; SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; &nbsp; int Size = 4; &nbsp; string DecoderNamespace = ""; &nbsp; list<Predicate&gt; Predicates = []; &nbsp; string DecoderMethod = ""; &nbsp; bit hasCompleteDecoder = 1; &nbsp; string Namespace = "RPP"; &nbsp; dag OutOperandList = (outs); &nbsp; dag InOperandL...

Hi Krzysztof, Today I try it on llvm9.0.0 version. &nbsp; def bos : RPPInstMMEMrr<OPC_STORE, &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; (outs), (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift), &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; !strconcat(opcodestr, ""), "$rs1,