search for: cpuidle

...ency; - cx->power = xen_cx->power; cx->target_residency = cx->latency * latency_factor; if ( cx->type == ACPI_STATE_C1 || cx->type == ACPI_STATE_C2 ) --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -96,7 +96,6 @@ static const struct cpuidle_state { char name[16]; unsigned int flags; unsigned int exit_latency; /* in US */ - int power_usage; /* in mW */ unsigned int target_residency; /* in US */ } *cpuidle_state_table; @@ -479,7 +478,6 @@ static int mwait_idle_cpu_init(struct no cx->type = cstate; cx->address =...

Folks, The second release candidate for Xen 3.4.0 is available at http://xenbits.xensource.com/xen-unstable.hg, tagged as ''3.4.0-rc2''. Please test! -- Keir _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

On Tue, Mar 22, 2011 at 06:03:28PM +0530, Trinabh Gupta wrote: > This patch implements a default cpuidle driver for xen. > Earlier pm_idle was flipped to default_idle. Maybe there > is a better way to ensure default_idle is called > without using this cpuidle driver. Please also CC the Xen devel mailing list (I did this for you) I couldn''t find it in the description, but I was wond...

cpuidle: Fix for timer_deadline==0 case After the scheduler timer became suspended before entering cpu idle state, the percpu timer_deadline is possible to be 0, i.e. no soft timer in the queue. This case will cause unexpected large residency percentage in C1 for the purely idle cpu. The fix is if timer_...

...11 08:43 AM, Len Brown wrote: > Why is this patch a step forward? Hi Len, I have basically moved the code for arch default and mwait idle from arch/x86/kernel/process.c to a driver. This was suggested by Venki (https://lkml.org/lkml/2010/10/19/460) as part of pm_idle cleanup and direct call of cpuidle_idle_call(). There is not much new code here. > >> +obj-$(CONFIG_X86) += default_driver.o > > BTW, that''s a pretty generic name for an x86 specific idle driver... > > I think that on builds that support intel_idle and acpi_idle, > every...

...then you can assume that the flood stopped and > invoke halt or whatever. > > That avoids all of that 'tunable and tweakable' x86 specific hackery and > utilizes common functionality which is mostly there already. here is some sample code. Poll for a while before enter halt in cpuidle_enter_state() If I get a reschedule event, then don't try to enter halt.? (I hope this is the right direction as Peter mentioned in another email) --- a/drivers/cpuidle/cpuidle.c +++ b/drivers/cpuidle/cpuidle.c @@ -210,6 +210,13 @@ int cpuidle_enter_state(struct cpuidle_device *dev, struct c...

When booting 2.6.37 (from kernel.org) under Xen 4.1, there are apparently issues with timer interrupts being delivered to the dom0. Repeatedly causing an interrupt (for example, the ACPI power button) will allow the system to boot, as does adding "clocksource=jiffies" to the kernel command line. This is only present under Xen, not when booting the same kernel on real hardware. When boot

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This patchset enable support for C1 mwait entry. [PATCH 1/3] dom0-C1-FFH.patch. It gets C1 information from ACPI table and pass it to Xen. [PATCH 2/3] add-idx-field.patch. This patch adds an idx field in the ''struct acpi_processor_cx''. It can simplify some coding lines. [PATCH 3/3] xen-C1-FFH.patch. It adds support for C1 FFH (mwait) entry. Meanwhile add timing for C1. The

[PATCH 1/2] Support multiple C3 states. There may be multiple ACPI C3 states mapped into different CPU C-states.So made some modification to support this case. [PATCH 2/2] Handle C2 LAPIC timer & TSC stop. ACPI C2 is quite possible mapped to CPU C3 or deeper state, so thinking from worst cases, enable C3 like entry/exit handling for C2 by default. Option ''lapic_timer_c2_ok''

ACPI C2 is quite possible mapped to CPU C3 or deeper state, so thinking from worst cases, enable C3 like entry/exit handling for C2 by default. Option ''lapic_timer_c2_ok'' can be used to select simple C2 entry/exit only if the user make sure that LAPIC tmr & TSC will not be stopped during C2. Signed-off-by: Wei Gang <gang.wei@intel.com>

Without this patch, while running on platforms on which the deepest C-state is C2, acpi_processor_idle fns will call into NULL function. BTW, made a little enhancement for keyhandler print-out to make it more readable. Signed-off-by: Wei Gang <gang.wei@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

Dom0 uses this hypercall to pass ACPI information to Xen. It is not very uncommon for more cpus to be listed in the ACPI tables than are present on the system, particularly on systems with a common BIOS for a 2 and 4 socket server varients. As Dom0 does not control the number of entries in the ACPI tables, and is required to pass everything it finds to Xen, reduce the ERR to an INFO.

.... I am using this on a dual CPU motherboard, it has two Xeon W3530 CPUs (i.e. family 6, model 26, stepping 5). I have also tested this with a single-CPU Core2 Quad Q6600 and the same situation occurs here, but the below output is of the W3530 Xeon system. While I''m not that familiar with CPUidle, one thing that seems to be not right is that the maximum idle state here is C3 while the processor should be able to reach as far as C7. Here is the snipped output of two commands: # xenpm get-cpufreq-states cpu id : 0 total P-states : 11 usable P-states : 11 current fre...

.... I am using this on a dual CPU motherboard, it has two Xeon W3530 CPUs (i.e. family 6, model 26, stepping 5). I have also tested this with a single-CPU Core2 Quad Q6600 and the same situation occurs here, but the below output is of the W3530 Xeon system. While I''m not that familiar with CPUidle, one thing that seems to be not right is that the maximum idle state here is C3 while the processor should be able to reach as far as C7. Here is the snipped output of two commands: # xenpm get-cpufreq-states cpu id : 0 total P-states : 11 usable P-states : 11 current fre...

On Thu, 16 Nov 2017, Quan Xu wrote: > On 2017-11-16 06:03, Thomas Gleixner wrote: > --- a/drivers/cpuidle/cpuidle.c > +++ b/drivers/cpuidle/cpuidle.c > @@ -210,6 +210,13 @@ int cpuidle_enter_state(struct cpuidle_device *dev, > struct cpuidle_driver *drv, > ??????????????? target_state = &drv->states[index]; > ??????? } > > +#ifdef CONFIG_PARAVIRT > +?????? paravirt_idle_...

On Wed, 15 Nov 2017, Peter Zijlstra wrote: > On Mon, Nov 13, 2017 at 06:06:02PM +0800, Quan Xu wrote: > > From: Yang Zhang <yang.zhang.wz at gmail.com> > > > > Implement a generic idle poll which resembles the functionality > > found in arch/. Provide weak arch_cpu_idle_poll function which > > can be overridden by the architecture code if needed. > >

On Wed, 15 Nov 2017, Peter Zijlstra wrote: > On Mon, Nov 13, 2017 at 06:06:02PM +0800, Quan Xu wrote: > > From: Yang Zhang <yang.zhang.wz at gmail.com> > > > > Implement a generic idle poll which resembles the functionality > > found in arch/. Provide weak arch_cpu_idle_poll function which > > can be overridden by the architecture code if needed. > >

...iang has been working on this to see if the abstraction can be improved, but I am by no means an ACPI expert - so feedback, guidance or input would be much appreciated. Liang: ACPI: processor: Don''t setup cpu idle driver and handler I think it can be actually dropped - now that disable_cpuidle() functionality exists and we use it? Kevin Tian (6): ACPI: processor: export necessary interfaces ACPI: processor: cache acpi_power_register in cx structure ACPI: processor: Don''t setup cpu idle driver and handler when we do not want them. ACPI: add processor dri...

...nel/irq/handle.c:195) handle_edge_irq+0x1cd/0x850 (kernel/irq/chip.c:622) handle_irq+0x105/0x2a0 (arch/x86/kernel/irq_64.c:69) ? __local_bh_enable+0x37/0x60 (kernel/softirq.c:139) do_IRQ+0x7d/0x1a0 (arch/x86/kernel/irq.c:213) common_interrupt+0x90/0x90 (arch/x86/entry/entry_64.S:452) RIP: 0010:cpuidle_enter_state+0x10d/0x7d0 (drivers/cpuidle/cpuidle.c:188) RSP: 0018:ffff88077228fdc0 EFLAGS: 00000202 ORIG_RAX: ffffffffffffff1e RAX: 0000000000000003 RBX: ffff8807761297b8 RCX: 000000000000001f RDX: 0000000000000004 RSI: 1ffff100eec23d1b RDI: ffffffff839ec680 RBP: ffff88077228fe18 R08: 0000000000012...