Possibly Parallel Threads
- [PATCH 2/2] CPUIDLE: Handle C2 LAPIC timer & TSC stop
- [PATCH 2/4] CPUIDLE: Avoid remnant LAPIC timer intr while force hpetbroadcast
- [PATCH] cpuidle: Fix for timer_deadline==0 case
- [PATCH]CPUIDLE: Initialize timer broadcast mechanism for C2
- [PATCH 0/2] CPUIDLE: fixings for multiple C3 & C2 LAPIC stop