Displaying 3 results from an estimated 3 matches for "cortexa".
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2012 Apr 18
1
[LLVMdev] llvmpipe on ARM CortexA-9
Hello,
Can i use llvmpipe for ARM cortexA-9 target ??
If it is already proven then send me any link or hint with details to test.
Thanks..
2016 Sep 19
3
[arm, aarch64] Alignment checking in interleaved access pass
Hi,
As a follow up to Patch D23646 <https://reviews.llvm.org/D23646>, I'm
trying to figure out if there should be an alignment check and what the
correct approach is.
Some background:
For stores, the pass turns:
%i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
<0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
store <12 x i32> %i.vec, <12 x i32>* %ptr
2016 Oct 10
2
[arm, aarch64] Alignment checking in interleaved access pass
...m and other ARM folks, could I get a recommendation
> on
> > reading material for performance tuning for the different ARM archs?
>
> ARM has a list of manuals on each core, including optimisation guides:
>
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.
> doc.set.cortexa/index.html
>
> cheers,
> --renato
>
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