search for: bitvectors

Hi, Doing some profiling of llc, I noticed that some bitvector operations took longer than usual. Then I noticed that too many copies of BitVector obejcts are created, even when such operations like &=, ^=, |= are performed on those bit vectors. I looked at the BitVector ADT implementation in BitVector.h and figured out that all assignment operations (except the usual assignment operator)

On Jan 23, 1:51 pm, Roman Levenstein <romix.l... at googlemail.com> wrote: > Hi, > > Doing some profiling of llc, I noticed that some bitvector operations > took longer than usual. Then I noticed that too many copies of > BitVector obejcts are created, even when such operations like &=, ^=, > |= are performed on those bit vectors. > > I looked at the BitVector ADT

Some time ago I developed a fast BitVector class to use in some research here. It uses expression templates to fuse operation loops and runs much faster than the existing BitVector for some important use-cases. It also has the ability to efficiently report if a BitVector's contents changed after some operation. For example: ETBitVector A = ... ETBitVector B = ... ETBitVector C = ... bool

On Apr 29, 2010, at 2:06 PM, Villmow, Micah wrote: > Ping. Anyone have any idea on how to fix this? Does your getAllocatableSet() return a BitVector that is at least getNumRegs() bits long? Otherwise this doesn't work: BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF); NonAllocatableRegs.flip();

Jakob, Here is my implementation of getAllocatableSet: BitVector AMDILRegisterInfo::getAllocatableSet(const MachineFunction& MF, const TargetRegisterClass *RC = NULL) const { BitVector Allocatable(getNumRegs()); Allocatable.clear(); return Allocatable; } Micah -----Original Message----- From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] Sent: Monday, May 03, 2010 9:52 AM To:

On 9/4/07, Devang Patel <dpatel at apple.com> wrote: > > On Sep 4, 2007, at 4:36 PM, Daniel Berlin wrote: > > [snip] > > Don't forget to update ProgrammersManual.html "Picking the Right > Data Structure for a Task" section. :) It doesn't talk about bitvector at all. I'm not sure whether i should add it to set like containers, or add a section

...uot;00100000010000010000000000000000" When I read this the bitVec field is not read properly. Instead, the value showing is "Inf" . How should i read this file? as.is/colclasses field in read function is not helping me. Is there any package that can do bitwise operation(and/or) on bitVectors. bitops seems to do that but I need output in bitvector format only. Thanks Fahim -- Fahim Mohammad Bioinforformatics Lab University of Louisville Louisville, KY, USA Ph: +1-502-409-1167 [[alternative HTML version deleted]]

Hi LLVMers, I am a PHD student in CS dept in UIUC, I am doing a project for Vikram's course, it is about PRE. I would like to know why you didn't choose SSAPRE in LLVM, since it seems to be more suitable for LLVM (it can operate directly on SSA form and avoid the conversion between SSA and bit-vector). Can anyone tell me the reason? Xuehai

Hi all, first up, big thanks to Dave for doing the hard work of porting Lucene. I have come to love Lucene through my Java work and was extremely pleased to find the Ferret project for Ruby. Now, I am tinkering with building the C extension using Visual Studio 2005. So far, I have had some success in getting something built and working in my Rails app (diffs attached). I am also encountering a

On Sep 4, 2007, at 4:36 PM, Daniel Berlin wrote: > Also, someone on IRC asked about the weird function naming > conventions. I know most of llvm uses mixedCase, but i copied the > style of BitVector, which has a weird mix. I'm happy to change it :) Yes please. By default, it is a good idea to follow llvm coding conventions instead of copying violation of coding style from

On Apr 2, 2008, at 10:11 PM, Xuehai Qian wrote: > Hi LLVMers, > I am a PHD student in CS dept in UIUC, I am doing a project for > Vikram's course, it is about PRE. I would like to know why you didn't > choose SSAPRE in LLVM, since it seems to be more suitable for LLVM (it > can operate directly on SSA form and avoid the conversion between SSA > and bit-vector). Can

On 9/4/07, Dan Gohman <djg at cray.com> wrote: > On Tue, Sep 04, 2007 at 10:35:10AM -0400, Daniel Berlin wrote: > > On 9/4/07, Dan Gohman <djg at cray.com> wrote: > > > On Fri, Aug 31, 2007 at 08:10:33PM -0400, Daniel Berlin wrote: > > > > + template <int ElementSize> > > > > + class SparseBitmap { > > > > > > Do you

Hi, I have an index where each document contains an untokenized ''url'' field. I would like to query the index for the most popular urls. In SQL I would do this via a Group By clause. Is there anything in Ferret that will do something similar? I found this discussion that proposed a solution involving TermEnums:

On Apr 4, 2008, at 8:28 PM, Daniel Berlin wrote: > On Fri, Apr 4, 2008 at 5:58 PM, Vikram S. Adve <vadve at cs.uiuc.edu> > wrote: >> >> >> Dan, >> >> Doesn't the paper also assume the invariant that phi operands are >> effectively dead after the Phi, which is true right after SSA is >> constructed, but potentially not after

..._MEMORY, HEAP_MEMORY. ALL_MEMORY contains GLOBAL_MEMORY, STACK_MEMORY, HEAP_MEMORY. e.g1: extern int * q; void f(int * p) { int a; *p = 0; //STMT1 *q = a; //STMT2 } For above case, both p and q pointed to ALL_MEMORY: p->ALL_MEMORY, q->ALL_MEMORY. And each STMT has two BitVectors to describe MayDef, MayUse. (I think the BitVector must be sparse, otherwise the alias-analysis module need too much memory to allocate for all BitVectors.) For STMT1, the MayDef={ALL_MEMORY}, MayUse={} For STMT2, the MayDef={ALL_MEMORY}, MayUse={'a'} --------------------- e.g2: exte...

On Apr 4, 2008, at 4:51 PM, Daniel Berlin wrote: > On Fri, Apr 4, 2008 at 2:38 AM, Bill Wendling <isanbard at gmail.com> > wrote: >> On Apr 2, 2008, at 10:11 PM, Xuehai Qian wrote: >>> Hi LLVMers, >>> I am a PHD student in CS dept in UIUC, I am doing a project for >>> Vikram's course, it is about PRE. I would like to know why you >>>

I've recently sync'd to a newer version of LLVM(Apple branch 2326 from Apple branch 2323.8) that changed the interface to addCommonCodeGenPasses which caused the default implementation to be executed instead of my overriding implementation. This default implementation has DeadMachineInstructionElim pass enabled, which is causing havoc with my backend. Before entering this pass, everything

Dale, Yeah that is correct, so that isn't the problem, not sure why I was thinking it is. The !MRI->use_no_dbg_empty(Reg) seems to be correct and the problem is LivePhysRegs[Reg] always returning false. I've looked into this more and there is a part where I'm working with physical registers. If there is a function call, there is a copy from virtual register space to the functions

On Fri, Apr 4, 2008 at 2:38 AM, Bill Wendling <isanbard at gmail.com> wrote: > On Apr 2, 2008, at 10:11 PM, Xuehai Qian wrote: > > Hi LLVMers, > > I am a PHD student in CS dept in UIUC, I am doing a project for > > Vikram's course, it is about PRE. I would like to know why you didn't > > choose SSAPRE in LLVM, since it seems to be more suitable for

On Fri, Apr 4, 2008 at 5:58 PM, Vikram S. Adve <vadve at cs.uiuc.edu> wrote: > On Apr 4, 2008, at 4:51 PM, Daniel Berlin wrote: > > > On Fri, Apr 4, 2008 at 2:38 AM, Bill Wendling <isanbard at gmail.com> > > wrote: > >> On Apr 2, 2008, at 10:11 PM, Xuehai Qian wrote: > >>> Hi LLVMers, > >>> I am a PHD student in CS dept in UIUC,