Displaying 15 results from an estimated 15 matches for "bitcasttoapint".
2014 May 05
3
[LLVMdev] get unsigned integer pattern for ConstantFP
What is the proper way to get the bit pattern associated with a ConstantFP?
The 32 bit pattern if MVT::f32 or pair of 32 bit patterns with MVT::f64 ?
Tia.
Reed
2018 Jan 19
2
computeKnownBits doesn't handle ISD::ConstantFP
SelectionDAG's computeKnownBits has no case for ConstantFP, e.g. Known.ones
= cast <ConstantFPSDNode>(Op)->getValueAFP ().bitcastToAPInt ();
I can't easily override this in target specific code. Can anyone see an
issue with submitting the patch to upstream?
Suggestions for an in tree target that could trigger this would be very
welcome.
Cheers
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2009 Mar 02
0
[LLVMdev] Please review the 2.5 release notes
..., i8*), but now
it means something different (probably that the return type is {i32,
i8*, i8*}, but I'm not sure).
- BinaryOperator::createAnd -> CreateAnd (and similarly for lots of
other createX functions)
- TargetData::getABITypeSize -> getTypePaddedSize
- APFloat::convertToAPInt -> bitcastToAPInt
I don't know if any of these count as "major".
Thanks,
Jay.
2015 Jan 20
2
[LLVMdev] Bug in InsertElement constant propagation?
Does anybody else have an opinion on this issue? I'm planning to submit a patch which would add a new get method for ConstantDataVector taking an ArrayRef<Constant*> and use that in the few places in constant propagation where convertToFloat is used.
Let me know if you think there is a more obvious way to do it.
Right now the only way to create a ConstantDataVector are those method:
2009 Mar 02
6
[LLVMdev] Please review the 2.5 release notes
Hi All,
Please review the 2.5 release notes here: http://llvm.org/docs/ReleaseNotes.html
Let me know if you have any additions, improvements, or see any
oversights. If you have commit access, please just directly change
the document.
The release is planned to go out in about 24 hours from now!
Thanks!
-Chris
2012 Feb 10
1
[LLVMdev] Prevent DAG combiner from changing "store ConstFP, addr" to integer store
...28:
break;
case MVT::f32:
if ((isTypeLegal(MVT::i32) && !LegalOperations &&
!ST->isVolatile()) ||
TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
bitcastToAPInt().getZExtValue(), MVT::i32);
return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
Ptr, ST->getPointerInfo(), ST->isVolatile(),
ST->isNonTemporal(), ST->getAlignment());
}
break;
-------------
What wou...
2011 Oct 10
2
[LLVMdev] Adding fixups and relocations late in code generation
...O.isReg()) {
unsigned Reg = MO.getReg();
unsigned RegNo = getMipsRegisterNumbering(Reg);
return RegNo;
} else if (MO.isImm()) {
return static_cast<unsigned>(MO.getImm());
} else if (MO.isFPImm()) {
return static_cast<unsigned>(APFloat(MO.getFPImm())
.bitcastToAPInt().getHiBits(32).getLimitedValue());
} else if (MO.isExpr()) {
const MCExpr *p_expr = MO.getExpr();
Fixups.push_back(MCFixup::Create(0, p_expr,
MCFixupKind(Mips::fixup_Mips_Branch_PCRel)));
}
return 0;
}
############################################
Later in MipsAsmBackend.cpp:App...
2015 Aug 10
2
Bug or expected behavior of APFloat class?
...{
SmallVector<char,10> strRep;
// FormatPrecision=0 means that the "natural precision" of the number is used
f.toString(strRep,/*FormatPrecision=*/0, /*FormatMaxPadding=*/0);
return std::string(strRep.begin(), strRep.end());
}
uint16_t getBits(APFloat f) {
APInt bits = f.bitcastToAPInt();
assert(bits.getActiveBits() <= 16);
return (uint16_t) (bits.getZExtValue() & 0xffff);
}
int main(int argc, char** argv) {
APFloat f(APFloat::IEEEhalf);
APFloat newF(APFloat::IEEEhalf);
f.convertFromString("0.3", APFloat::rmTowardZero);
outs() << "f bits:...
2012 Mar 05
1
[LLVMdev] printing hex format for floating point number
Hi,
I am trying to print a hex value ( 4111999A for 9.1) for a corresponding
floating point number. The routine convertToHexString in APFFloat class
only prints in C99 Floating point hexagondecimal constant (eg 1.e00000p3).
Without writing my own routine, how do I get to print the hexadecimal
representation for a floating point value?
Sirish
--
Qualcomm Innovation Center, Inc is a member
2018 Jan 19
0
computeKnownBits doesn't handle ISD::ConstantFP
...k.
On 19 Jan 2018 18:53, "Friedman, Eli" <efriedma at codeaurora.org> wrote:
On 1/19/2018 4:01 AM, Jon Chesterfield via llvm-dev wrote:
> SelectionDAG's computeKnownBits has no case for ConstantFP, e.g.
> Known.ones = cast <ConstantFPSDNode>(Op)->getValueAFP ().bitcastToAPInt
> ();
>
This was added in https://reviews.llvm.org/rL316831 .
-Eli
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux
Foundation Collaborative Project
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2011 Oct 10
0
[LLVMdev] Adding fixups and relocations late in code generation
...Reg();
>
> unsigned RegNo = getMipsRegisterNumbering(Reg);
> return RegNo;
>
> } else if (MO.isImm()) {
> return static_cast<unsigned>(MO.getImm());
> } else if (MO.isFPImm()) {
> return static_cast<unsigned>(APFloat(MO.getFPImm())
> .bitcastToAPInt().getHiBits(32).getLimitedValue());
> } else if (MO.isExpr()) {
> const MCExpr *p_expr = MO.getExpr();
> Fixups.push_back(MCFixup::Create(0, p_expr,
> MCFixupKind(Mips::fixup_Mips_Branch_PCRel)));
> }
> return 0;
> }
>
> #####################################...
2014 Jun 08
2
[LLVMdev] [llvm] r210424 - Revert "Do materialize for floating point"
...EmitInstStore(Mips::SW, SrcReg, Addr.Base.Reg, Addr.Offset);
> return true;
> }
>
> @@ -234,22 +229,6 @@ bool MipsFastISel::TargetSelectInstructi
> }
>
> unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
> - int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
> - if (VT == MVT::f32) {
> - const TargetRegisterClass *RC = &Mips::FGR32RegClass;
> - unsigned DestReg = createResultReg(RC);
> - unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
> - EmitInst(Mips::MTC1, DestReg).addReg(TempR...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...PInt(Cst).trunc(NVTBits), NVT);
- Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
- break;
- }
- case ISD::ConstantFP: {
- ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
- if (CFP->getValueType(0) == MVT::ppcf128) {
- APInt api = CFP->getValueAPF().bitcastToAPInt();
- Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
- MVT::f64);
- Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
- MVT::f64);
- break;
- }
- Lo = ExpandConstantFP(CFP, fal...