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llvm/lib/Target/X86/X86InstrInfo.td: class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> : Instruction { .... dag OperandList = ops; string AsmString = AsmStr; } def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov{l} {$src, $dst|$dst, $src}">; I cannot find any document on initializing the 'dag' type variable, and I cannot understand the syntax of "asmstring" either. how do...

The macro $src, $dest used in Instruction::AsmString must be "declared" in Instruction::OperandList, right? $$ has special meaning? On 5/6/05, Chris Lattner <sabre at nondot.org> wrote: > On Fri, 6 May 2005, Tzu-Chien Chiu wrote: > > llvm/lib/Target/X86/X86InstrInfo.td: > > class X86Inst<bits<8> opcod, Forma...

On Fri, 6 May 2005, Tzu-Chien Chiu wrote: > llvm/lib/Target/X86/X86InstrInfo.td: > class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string > AsmStr> : Instruction { > .... > dag OperandList = ops; > string AsmString = AsmStr; > } > > def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), > "mov{l} {$src, $dst|$dst, $src}">; > > I cannot find any document on initializing the 'dag' type variable, > and I cannot understand the syntax of &quot...

On Fri, Jan 29, 2016 at 10:22 AM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 1/28/2016 8:11 PM, Rail Shafigulin via llvm-dev wrote: > >> >> Would anyone be able to figure out why this is happening? I can provide >> more code if needed. >> > > The error message should show what types have been inferred so far. > > You

...n Silva wrote: > I think you're missing the template args for `FRRR16_ins` in the first > argument. The switch in TGParser::ParseType() doesn't cover the case > of types with template args though... which makes me wonder what is > going on inside of TableGen to make `I.f` and `I.AsmString` valid... > > --Sean Silva > > On Mon, Jul 2, 2012 at 8:07 PM, reed kotler<rkotler at mips.com> wrote: >> I've filed the following bug. Maybe I'm doing something stupid here or >> maybe someone knows of a workaround. >> >> The following fragment fr...

...ntation which has the same problem. class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>; I think that the problem has to do with t...

...gt;> I think you're missing the template args for `FRRR16_ins` in the first >> argument. The switch in TGParser::ParseType() doesn't cover the case >> of types with template args though... which makes me wonder what is >> going on inside of TableGen to make `I.f` and `I.AsmString` valid... >> >> --Sean Silva >> >> On Mon, Jul 2, 2012 at 8:07 PM, reed kotler<rkotler at mips.com> wrote: >>> >>> I've filed the following bug. Maybe I'm doing something stupid here or >>> maybe someone knows of a workaround. >&g...

...I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconc...

...ot;\t$rz, $rx, $ry"), pattern, itin>; class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // tablegen bug: should be I.OutOperandList, I.InOperandList, I.AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], I.Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; }

...SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } On 07/05/2012 03:11 PM, reed kotler wrote: > I think that what I did originally should have worked and the...

> On Jan 29, 2016, at 13:25, Rail Shafigulin via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details: > > defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>; > > multiclass SF<bits<5> op2Val, string asmstr, PatLeaf

...I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconc...

...st field in the following example: class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { field bits<32> Inst; let Namespace = "SP"; bits<2> op; let Inst{31-30} = op; dag OutOperandList = outs; dag InOperandList = ins; let AsmString = asmstr; let Pattern = pattern; } And define the instruction class of ported target as: class Instxxx<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "xxx"; dag OutOperandList = outs; dag InOperandList = ins; let AsmString...

Hi All, Is it possible to initialize(set up) register attributes when we define an instruction? like if a register is defined like this: " class SC_Register<bits<8> register_num, REG_FLAG SC_X, REG_FLAG SC_Y, REG_FLAG SC_Z, REG_FLAG SC_W, string asmstr> : Register<asmstr> { let HWEncoding{7-0} =

...t<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> > : Instruction { > let Namespace = "AMDIL"; > dag OutOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0...

I'm starting to look into binary instruction encodings in TableGen, and I'm a bit confused on how the instruction fields are populated. Perhaps I'm just being dense, but I cannot see how SDAG operands are translated into the encoding fields. Can someone please explain the following snippet from the PPC back-end. The AND instruction in PPC is defined as: 1011 def AND :

I think you're missing the template args for `FRRR16_ins` in the first argument. The switch in TGParser::ParseType() doesn't cover the case of types with template args though... which makes me wonder what is going on inside of TableGen to make `I.f` and `I.AsmString` valid... --Sean Silva On Mon, Jul 2, 2012 at 8:07 PM, reed kotler <rkotler at mips.com> wrote: > I've filed the following bug. Maybe I'm doing something stupid here or > maybe someone knows of a workaround. > > The following fragment from mips16 (not yet checked into ma...

...op3; let Inst{18-14} = rs1; } class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { field bits<32> Inst; let Namespace = "SP"; bits<2> op; let Inst{31-30} = op; dag OutOperandList = outs; dag InOperandList = ins; let AsmString = asmstr; let Pattern = pattern; } I cannot see how the values simm13, rd, and rs1 are actually set. While in some places in the .td file there are instructions prefixed with "let rd = ...", the store instructions are not. How do the register numbers/immediates get from $src and $add...

...t<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> > : Instruction { > let Namespace = "AMDIL"; > dag OutOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0...

On Tue, Jul 24, 2012 at 3:59 PM, Tom Stellard <thomas.stellard at amd.com>wrote: > On Tue, Jul 24, 2012 at 03:25:14PM -0400, Justin Holewinski wrote: > > I'm starting to look into binary instruction encodings in TableGen, and > I'm > > a bit confused on how the instruction fields are populated. Perhaps I'm > > just being dense, but I cannot see how SDAG