Displaying 20 results from an estimated 370 matches for "arsenault".
2013 Dec 05
3
[LLVMdev] Loads moving across barriers
On 12/04/2013 04:29 PM, Andrew Trick wrote:
> On Dec 4, 2013, at 3:33 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote:
>
>> On 11/11/2013 03:13 PM, Andrew Trick wrote:
>>> On Nov 9, 2013, at 1:39 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>>>
>>>> On Nov 9, 2013, at 3:14 AM, Chandler Carruth <chandlerc at google.com>...
2013 Dec 05
0
[LLVMdev] Loads moving across barriers
On Dec 4, 2013, at 5:19 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote:
> On 12/04/2013 04:29 PM, Andrew Trick wrote:
>> On Dec 4, 2013, at 3:33 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote:
>>
>>> On 11/11/2013 03:13 PM, Andrew Trick wrote:
>>>> On Nov 9, 2013, at 1:39 P...
2015 Jan 29
4
[LLVMdev] RFC: Add ISD nodes for mad
> On Jan 28, 2015, at 3:47 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> ----- Original Message -----
>> From: "Matt Arsenault" <Matthew.Arsenault at amd.com>
>> To: "llvmdev at cs.uiuc.edu" <LLVMdev at cs.uiuc.edu>
>> Sent: Wednesday, January 28, 2015 1:52:59 PM
>> Subject: [LLVMdev] RFC: Add ISD nodes for mad
>>
>> Hi,
>>
>> I would like to add an ISD...
2015 Jan 27
2
[LLVMdev] Making a CopyToReg/CopyFromReg into a zext/sext?
Thanks for getting back to me.
So those nodes record if the type has already been expanded from a narrower
type. Can you elaborate how I could use these to help? Again, I'm pretty
unfamiliar with the SDNodes.
Thanks.
On Tue, Jan 27, 2015 at 3:22 PM, Matt Arsenault <Matthew.Arsenault at amd.com>
wrote:
> On 01/27/2015 12:16 PM, Ryan Taylor wrote:
>
> I have a CopyToReg that is copying from different size types, what's the
> best way to change that to a zext or sext node based on signed or unsigned?
>
> I'm fairly unfamiliar...
2019 Apr 18
2
Disable combining of loads and stores in instcombine
IIRC it’s not strictly possible to determine what array a load/store is based on. I don’t believe the decomposition is always possible, as information is lost when accesses are combined.
Neil
On Apr 17, 2019, 12:31 PM -0700, Arsenault, Matthew <Matthew.Arsenault at amd.com>, wrote:
> This is really a codegen problem. You can decompose the load/store however you like in the backend. InstCombine should still combine the loads as a canonicalization.
>
> -Matt
>
> From: llvm-dev <llvm-dev-bounces at lists.llv...
2019 Oct 07
2
LiveInterval error with 2 dead defs
...at. It should be added where it’s missing.
--
Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development
From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Quentin Colombet via llvm-dev
Sent: Monday, September 9, 2019 7:17 PM
To: Arsenault, Matthew <Matthew.Arsenault at amd.com>
Cc: llvm-dev <llvm-dev at lists.llvm.org>
Subject: [EXT] Re: [llvm-dev] LiveInterval error with 2 dead defs
Hi Matt,
The expectation is that each LiveInterval should only have values that are connected somehow, otherwise these should be split in...
2015 Jan 27
4
[LLVMdev] Making a CopyToReg/CopyFromReg into a zext/sext?
...that the SelDAG was the easiest and
cleanest way to do this.
I can change the mov to an extension MI in the .td file; however, I can't
tell at that point whether it's a sext or a zext, so it seemed the SelDAG
was the better place to fix this.
Thanks.
On Tue, Jan 27, 2015 at 3:38 PM, Matt Arsenault <Matthew.Arsenault at amd.com>
wrote:
> On 01/27/2015 12:28 PM, Ryan Taylor wrote:
>
> Thanks for getting back to me.
>
> So those nodes record if the type has already been expanded from a
> narrower type. Can you elaborate how I could use these to help? Again, I'm
&...
2014 Jul 10
2
[LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!
..., @llvm.convert.to.fp16 can compile successfully. However, the runtime is not right.
+ setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);+ setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
Robin
yalong at multicorewareinc.com
From: Andrea Di BiagioDate: 2014-07-09 14:20To: Matt ArsenaultCC: yalong at multicorewareinc.com; Kevin Qin; llvmdevSubject: Re: [LLVMdev] Help!!!!Help!!!! " LLVM ERROR: Cannot select: 0x9fc9680: i32 = fp32_to_fp16 0x9fc0750 [ID=16] " problem!!!!!!!!!!!!!!!!!!Not sure if this can help, but
if you really really want to have minimal half float support...
2014 Jul 08
2
[LLVMdev] LLVM commit 410f38e01597120b41e406ec1cea69127463f9e5
On 07/08/2014 03:20 PM, Matt Arsenault wrote:
> Alternatively maybe this should only be done if the setcc type is the
> same as the sext result?
I think we should actually do this. If you need to convert the setcc
result after, you aren't really gaining anything by doing this
transformation
-------------- next part --------...
2015 Aug 08
2
[RFC] BasicAA considers address spaces?
On Aug 7, 2015, at 8:28 PM, Hal Finkel <hfinkel at anl.gov<mailto:hfinkel at anl.gov>> wrote:
________________________________
From: "Jingyue Wu" <jingyue at google.com<mailto:jingyue at google.com>>
To: "Matt Arsenault" <Matthew.Arsenault at amd.com<mailto:Matthew.Arsenault at amd.com>>
Cc: llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>, "Hal Finkel" <hfinkel at anl.gov<mailto:hfinkel at anl.gov>>, "Justin Holewinski" <jholewinski at nvidia....
2015 Aug 07
2
[RFC] BasicAA considers address spaces?
On Fri, Aug 7, 2015 at 12:01 PM, Matt Arsenault <Matthew.Arsenault at amd.com>
wrote:
> On 08/07/2015 11:35 AM, Jingyue Wu wrote:
>
> + the new llvm-dev
>
> On Fri, Aug 7, 2015 at 11:30 AM, Jingyue Wu <jingyue at google.com> wrote:
>
>> Hi folks,
>>
>> Unsurprisingly, leveraging the fact that cert...
2013 Dec 21
2
[LLVMdev] Loads moving across barriers
On Dec 4, 2013, at 8:25 PM, Andrew Trick <atrick at apple.com> wrote:
>
> On Dec 4, 2013, at 5:19 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote:
>
>> On 12/04/2013 04:29 PM, Andrew Trick wrote:
>>> On Dec 4, 2013, at 3:33 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote:
>>>
>>>> On 11/11/2013 03:13 PM, Andrew Trick wrote:
>>>>>...
2014 Mar 26
3
[LLVMdev] Reducing Generic Address Space Usage
On Tue, Mar 25, 2014 at 3:21 PM, Matt Arsenault
<Matthew.Arsenault at amd.com>wrote:
> On 03/25/2014 02:31 PM, Jingyue Wu wrote:
>
>
> However, we have three concerns on this:
> a) I doubt this optimization is valid for all targets, because LLVM
> language reference (
> http://llvm.org/docs/LangRef.html#addrspacecast...
2013 Nov 09
4
[LLVMdev] Loads moving across barriers
----- Original Message -----
> Hi Matt,
>
> On Nov 8, 2013, at 1:14 PM, Matt Arsenault
> <Matthew.Arsenault at amd.com> wrote:
>
> > Both of these I think sort of went in the wrong direction and
> > talked specifically about the semantics of the atomic instructions
> > (fence in particular), which isn't the real question. Is noalias
> > suppos...
2015 Jul 03
2
[LLVMdev] Declare multiple data type for a register class in tblegen
Thanks. I'm gonna try tomorrow and let you know.
On Thu, Jul 2, 2015 at 6:51 PM Matt Arsenault <Matthew.Arsenault at amd.com>
wrote:
> On 07/02/2015 06:41 PM, Xiaochu Liu wrote:
> > Hi Matt,
> >
> > I did call addRegisterClass in TargetLowering for all the possible
> > types in the register. And for typecasting instructions (i32 to i64),
> > it works....
2013 Dec 04
2
[LLVMdev] Loads moving across barriers
On 11/11/2013 03:13 PM, Andrew Trick wrote:
> On Nov 9, 2013, at 1:39 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>
>> On Nov 9, 2013, at 3:14 AM, Chandler Carruth <chandlerc at google.com> wrote:
>>
>>> Perhaps you're instead trying to say that with certain address spaces "noalias" (and by inference, "restrict" at the la...
2016 Aug 18
2
extract_vector_elt type mismatch?
On 18 August 2016 at 10:46, Matt Arsenault via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> I think this is just intended as a quirk for some weird targets that have a
> legal vector type, but the scalar type itself is not legal, so it requires
> an implicit extension when extracting it.
I think it's a pretty common RI...
2019 Sep 09
2
LiveInterval error with 2 dead defs
Hi,
I’m hitting a machine verifier error in a trivial testcase which I don’t understand. There are 2 dead defs of the same register:
---
name: multiple_connected_compnents_dead
tracksRegLiveness: true
body: |
bb.0:
dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
...
The live intervals look OK to me with 1 valno
2013 Aug 07
4
[LLVMdev] Address space extension
On 08/07/2013 03:52 PM, Michele Scandale wrote:
>
> In the opencl specification is said that the four address spaces are
> disjoint, so my conclusion of non aliasing with the others.
In OpenCL 2.0, you can cast between the generic address space and
global/local/private, so there's also that to consider.
2013 Dec 05
0
[LLVMdev] Loads moving across barriers
On Dec 4, 2013, at 3:33 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote:
> On 11/11/2013 03:13 PM, Andrew Trick wrote:
>> On Nov 9, 2013, at 1:39 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>>
>>> On Nov 9, 2013, at 3:14 AM, Chandler Carruth <chandlerc at google.com> wrote:
>>&g...