Displaying 8 results from an estimated 8 matches for "amdilisd".
2010 Nov 08
2
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...te some tablegen code that has no return value, the instruction gets deleted.
Here is my profile/node/pattern.
Profile:
def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [
SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
]>;
Node:
def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtomNoRet, [SDNPHasChain]>;
Pattern:
def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,
"_id($id)", atom_g_add_noret>;
I am Lowering INTRINSIC_W_CHAIN to lower from @llvm.amdil.atomic.add.gi32.noret to the correct instruction with th...
2010 Nov 08
1
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...ctly.
I've attached a before and after instruction creation of DAG.dump().
This is the instruction I'm trying to match:
0x8502b88: i32,ch = llvm.AMDIL.atomic.add.gi32.noret 0x8502a78, 0x8502b00, 0x8502280, 0x8502eb8 [ORD=6] [ID=19]
And I generate this instruction:
0x8503160: i32 = AMDILISD::ATOM_G_ADD_NORET 0x8502a78, 0x8502280, 0x8502eb8, 0x8502f40
0x8502a78: <multiple use>
0x8503608: i32,ch = merge_values 0x8503160, 0x8502a78
What I'm trying to figure out is how I can generate this without the merge_values:
0x8503160: i32,ch = AMDILISD::ATOM_G_ADD_NORET 0x8502a78,...
2010 Nov 08
0
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...n ARMInstrInfo.td).
Regards,
Jim
>
> Here is my profile/node/pattern.
> Profile:
> def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [
> SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
> ]>;
> Node:
> def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtomNoRet, [SDNPHasChain]>;
>
> Pattern:
> def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,
> "_id($id)", atom_g_add_noret>;
>
>
> I am Lowering INTRINSIC_W_CHAIN to lower from @llvm.amdil.atomic.add.gi32.no...
2008 Sep 23
2
[LLVMdev] Store patterns accepting i32 only?
...enerates the code, it only generates the code
for i32 only.
def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>;
def MEM : Operand<i32> {
let PrintMethod = "printMemOperand";
let MIOperandInfo = (ops GPR, GPR);
}
def global_st : SDNode<"AMDILISD::GLOBAL_STORE", SDTStore,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def global_store : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr), [{
return isGlobalStore(dyn_cast<StoreSDNode>(N));
}]>;
def GLOBALSTORE : OneInOneOut<IL_OP...
2011 Mar 31
3
[LLVMdev] Assert in VerifySDNode
...out what I am generating.
What I generate has worked fine from LLVM version 2.4 until now without causing any issues.
This is occuring while I am attempting to lower a vector extract elt to a custom SDNode that my backend understands.
I am creating the instruction like as follows:
Op = DAG.getNode(AMDILISD::VEXTRACT,
Op.getDebugLoc(), Op.getValueType(),
Op.getOperand(0),
DAG.getTargetConstant(dyn_cast<ConstantSDNode>(Op.getOperand(1)->getZExtValue() + 1), MVT::i32));
The custom backend instruction is defined as follows:
def SDTIL_GenVecExtract : SDTypeProfile<1, 2...
2008 Sep 23
0
[LLVMdev] Store patterns accepting i32 only?
...ates the
> code for i32 only.
>
> def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>;
> def MEM : Operand<i32> {
> let PrintMethod = "printMemOperand";
> let MIOperandInfo = (ops GPR, GPR);
> }
> def global_st : SDNode<"AMDILISD::GLOBAL_STORE", SDTStore,
> [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
>
> def global_store : PatFrag<(ops node:$val, node:$ptr),
> (st node:$val, node:$ptr), [{
> return isGlobalStore(dyn_cast<StoreSDNode>(N));
> }]>;
> def GLOBALSTOR...
2008 Nov 18
1
[LLVMdev] 32 bit boolean results
You can tell LLVM that you have "sign extended" setCC results (all
ones).
Dan
On Nov 18, 2008, at 5:33 PM, Eli Friedman wrote:
> On Tue, Nov 18, 2008 at 1:56 PM, Villmow, Micah
> <Micah.Villmow at amd.com> wrote:
>> The IR produces correct results, but my backend does not and the
>> only thing
>> I can think of is that the IR is treating the
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...erand(1));
> + case AMDGPUIntrinsic::AMDGPU_lrp:
> + return LowerIntrinsicLRP(Op, DAG);
> + case AMDGPUIntrinsic::AMDIL_fraction:
> + return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
> + case AMDGPUIntrinsic::AMDIL_mad:
> + return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1),
> + Op.getOperand(2), Op.getOperand(3));
> + case AMDGPUIntrinsic::AMDIL_max:
> + return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
> + Op.getOperand(2));
&g...