Displaying 6 results from an estimated 6 matches for "afrm".
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2016 Feb 04
2
New register class and patterns
...$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;
bits<16> imm;
let Inst{25-21} = op2;
let Inst{20-16} = rA;
let Inst{15-0} = imm;
let format = AFrm;
let op2 = op2Val;
}
--
Rail Shafigulin
Software Engineer
Esencia Technologies
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2016 Feb 19
3
Failure to match a DAG after a minor pattern change in a custom Target
...rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Esenciasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;
bits<16> imm;
let Inst{25-21} = op2;
let Inst{20-16} = rA;
let Inst{15-0} = imm;
let format = AFrm;
let op2 = op2Val;
}
defm SFLTS : SF<0xc, "l.sflts", Esencia_CC_LT>;
========================= Modified Code
=====================================
def SDT_EsenciaSetFlag : SDTypeProfile<1, 3, [SDTCisSameAs<1, 2>]>;
def Esenciasetflag : SDNode<"Esen...
2016 Jan 29
2
New register class and patterns
I've added a new register class to my target, but haven't used any of the
new registers in any of the instructions. However when I compile llvm I get
the following error:
In SFEQ_ri: Could not infer all types in pattern
Curiously all the instructions where this error occurs are the set flag
instructions (flags like zero, less than, greater than etc).
Would anyone be able to figure out
2016 Feb 04
2
New register class and patterns
...$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;
bits<16> imm;
let Inst{25-21} = op2;
let Inst{20-16} = rA;
let Inst{15-0} = imm;
let format = AFrm;
let op2 = op2Val;
}
multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> {
def _rr : SF_RR<op2Val, asmstr, Cond>;
def _ri : SF_RI<op2Val, asmstr, Cond>;
}
defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>;
--
Rail Shafigulin
Software Engineer
Es...
2016 Feb 03
2
New register class and patterns
On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>
> On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote:
>
> def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
>
>
> I think for setting an implicit register, you still need to have 1 result
> here.
>
> If you look at
2016 Jan 29
3
New register class and patterns
...$rA, s16imm:$imm),
!strconcat(asmstr, "i\t$rA, $imm"),
[(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> {
bits<5> op2;
bits<5> rA;
bits<16> imm;
let Inst{25-21} = op2;
let Inst{20-16} = rA;
let Inst{15-0} = imm;
let format = AFrm;
let op2 = op2Val;
}
I would appreciate any feedback.
--
Rail Shafigulin
Software Engineer
Esencia Technologies
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