search for: addiu

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2013 Feb 20
3
[LLVMdev] Is va_arg correct on Mips backend?
...bc" .text .globl _Z5sum_iiz .align 2 .type _Z5sum_iiz, at function .set nomips16 # @_Z5sum_iiz .ent _Z5sum_iiz _Z5sum_iiz: .cfi_startproc .frame $sp,64,$ra .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro .set noat # BB#0: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -64 $tmp2: .cfi_def_cfa_offset 64 sw $ra, 60($sp) # 4-byte Folded Spill $tmp3: .cfi_offset 31, -4 addu $gp, $2, $25 sw $7, 76($sp) sw $6, 72($sp) sw $5, 68($sp) lw $3, %got(__stack_chk_guard)($gp) lw $1, 0($3) sw $1, 56($sp) sw $4, 52($sp...
2013 Feb 20
0
[LLVMdev] Is va_arg correct on Mips backend?
...Z5sum_iiz, at function > .set nomips16 # @_Z5sum_iiz > .ent _Z5sum_iiz > _Z5sum_iiz: > .cfi_startproc > .frame $sp,64,$ra > .mask 0x80000000,-4 > .fmask 0x00000000,0 > .set noreorder > .set nomacro > .set noat > # BB#0: > lui $2, %hi(_gp_disp) > addiu $2, $2, %lo(_gp_disp) > addiu $sp, $sp, -64 > $tmp2: > .cfi_def_cfa_offset 64 > sw $ra, 60($sp) # 4-byte Folded Spill > $tmp3: > .cfi_offset 31, -4 > addu $gp, $2, $25 > sw $7, 76($sp) > sw $6, 72($sp) > sw $5, 68($sp) > lw $3, %got(__stack_chk_guard)($gp...
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
...c8fc8:1, 0x88c88f8, 0x88c9540 => 0x88c8970: ch = BNE 0x88c8fc8, 0x88c9060, 0x88c9540, 0x88c8fc8:1 Selecting: 0x88c9540: ch = BasicBlock <cond_false 0x88c7db8> => 0x88c9540: ch = BasicBlock <cond_false 0x88c7db8> Selecting: 0x88c9060: i32 = Constant <2> => 0x88c9060: i32 = ADDiu 0x88c9360, 0x88c88f8 Selecting: 0x88c8fc8: i32,ch = load 0x88c8f30, 0x88c8d70, 0x88c8dd8 => 0x88c8a98: i32,ch = LW 0x88c8a30, 0x88c89c8, 0x88c8f30 Selecting: 0x88c8f30: ch = store 0x88c8e30, 0x88c9160, 0x88c8ec8, 0x88c8dd8 => 0x88c8b10: ch = SW 0x88c9160, 0x88c8a30, 0x88c8fc8, 0x88c8e30 Selec...
2016 Oct 15
3
How to remove memcpy
...%1 = bitcast [10 x [10 x float]]* %b to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* %1, i8* bitcast ([10 x [10 x float]]* @main.b to i8*), i32 400, i32 4, i1 false) store i32 0, i32* %sum, align 4 *Assembly File Snip:* # BB#0: # %entry lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -1664 sw $ra, 1660($sp) # 4-byte Folded Spill sw $fp, 1656($sp) # 4-byte Folded Spill sw $17, 1652($sp) # 4-byte Folded Spill sw $16, 1648($sp) # 4-byte Folded Spill move $fp, $sp addu $17, $2, $25 lw $1, %got($main.a)($17) a...
2013 Feb 19
0
[LLVMdev] Is va_arg correct on Mips backend?
Which part of the generated code do you think is not correct? Could you be more specific? I compiled this program with clang and ran it on a mips board. It returns the expected result (21). On Tue, Feb 19, 2013 at 4:15 AM, Jonathan <gamma_chen at yahoo.com.tw> wrote: > I check the Mips backend for the following C code fragment compile result. > It seems not correct. Is it my
2013 Feb 19
2
[LLVMdev] Is va_arg correct on Mips backend?
I check the Mips backend for the following C code fragment compile result. It seems not correct. Is it my misunderstand or it's a bug. //ch8_3.cpp #include <stdarg.h> int sum_i(int amount, ...) { int i = 0; int val = 0; int sum = 0; va_list vl; va_start(vl, amount); for (i = 0; i < amount; i++) { val = va_arg(vl, int); sum += val; } va_end(vl);
2013 Feb 27
2
[LLVMdev] Mips backend 3.2 va_arg possible bug
...arch=mipsel -relocation-model=static -asm-verbose -mattr=+condmov,-muldivadd,+single-float,-fp64,+o32,-bitcount " command in function we report the values of a long long value then an integer value and then again a long long so the problem is that in the test2 function there is an addiu $3, $2, 4 that causes the third long long value to be read from wrong address. mipsel.s <http://llvm.1065342.n5.nabble.com/file/n55498/mipsel.s> .set nomacro # BB#0: # %entry addiu $sp, $sp, -24 sw $ra, 20($sp)...
2012 Dec 28
1
[LLVMdev] [PATCH] LLVM build failure on OpenBSD/mips64
..."MipsCompilationCallback:\n" ".ent " ASMPREFIX "MipsCompilationCallback\n" - ".frame $sp, 32, $ra\n" + ".frame $29, 32, $31\n" ".set noreorder\n" - ".cpload $t9\n" + ".cpload $25\n" - "addiu $sp, $sp, -64\n" + "addiu $29, $29, -64\n" ".cprestore 16\n" // Save argument registers a0, a1, a2, a3, f12, f14 since they may contain @@ -115,35 +115,35 @@ // concerned. We also need to save the ra register since it contains the // original return...
2011 Nov 11
4
[LLVMdev] How to get MIPS from clang + llvm ?
...SOWh0.s:11: Error: unknown pseudo-op: `.mask' /tmp/cc-9SOWh0.s:12: Error: unknown pseudo-op: `.fmask' /tmp/cc-9SOWh0.s:13: Error: expected comma after "noreorder" /tmp/cc-9SOWh0.s:14: Error: expected comma after "nomacro" /tmp/cc-9SOWh0.s:15: Error: no such instruction: `addiu $sp,$sp,-48' /tmp/cc-9SOWh0.s:16: Error: no such instruction: `sw $ra,44($sp)' /tmp/cc-9SOWh0.s:17: Error: no such instruction: `sw $fp,40($sp)' /tmp/cc-9SOWh0.s:18: Error: no such instruction: `addu $fp,$sp,$zero' /tmp/cc-9SOWh0.s:19: Error: no such instruction: `sw $zero,32($fp)...
2013 Feb 28
0
[LLVMdev] Mips backend 3.2 va_arg possible bug
...el=static -asm-verbose > -mattr=+condmov,-muldivadd,+single-float,-fp64,+o32,-bitcount " command > > in function we report the values of a long long value then an integer > value > and then again a long long > so the problem is that in the test2 function there is an addiu > $3, $2, 4 > that causes the third long long value to be read from wrong address. > mipsel.s <http://llvm.1065342.n5.nabble.com/file/n55498/mipsel.s> > > .set nomacro > # BB#0: # %entry > addiu $sp, $sp, -24 >...
2013 Feb 04
2
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
...ebug.abi32 .previous .file "helloworld.ll" .text .globl main .align 2 .type main, at function .set nomips16 # @main .ent main main: .frame $sp,24,$ra .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro .set noat # BB#0: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -24 sw $ra, 20($sp) # 4-byte Folded Spill addu $gp, $2, $25 lw $1, %got($str)($gp) lw $25, %call16(puts)($gp) jalr $25 addiu $4, $1, %lo($str) addiu $2, $zero, 0 lw $ra, 20($sp) # 4-byte Folded Reload jr $ra addiu $sp, $sp, 24...
2012 Nov 11
2
[LLVMdev] Tracing nodes in selectionDAG to final code...
...ug.abi32 .previous .file "hello.bc" .text .globl main .align 2 .type main, at function .set nomips16 # @main .ent main main: .cfi_startproc .frame $sp,32,$ra .mask 0x80000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro # BB#0: # %entry addiu $sp, $sp, -32 $tmp2: .cfi_def_cfa_offset 32 sw $ra, 28($sp) # 4-byte Folded Spill $tmp3: .cfi_offset 31, -4 lui $2, %hi(__gnu_local_gp) addiu $2, $2, %lo(__gnu_local_gp) sw $2, 16($sp) sw $zero, 24($sp) lui $2, %hi($.str) addiu $4, $2, %lo($.str) jal printf nop addiu $2, $zero, 0 lw $ra,...
2013 Sep 02
0
[LLVMdev] .globl
...t), then the program will > run very slow if compiled in -fPIC and linked as C++. It seems to be > stuck in the loader (probably doing dynamic binding over and over again). This might or might not be related, but I notice that for the attached testcase, LLVM emits: lui $2, %hi(_gp_disp) addiu $2, $2, %lo(_gp_disp) addiu $sp, $sp, -32 $tmp2: .cfi_def_cfa_offset 32 sw $ra, 28($sp) # 4-byte Folded Spill sw $18, 24($sp) # 4-byte Folded Spill sw $17, 20($sp) # 4-byte Folded Spill sw $16, 16($sp) # 4-byte Folded Spill $tmp3: .cfi_offset 31, -...
2012 Jan 18
2
[LLVMdev] Question about isel patterns
...as short as possible, so simply partitioning the immediate into four 16-bit parts will not work. Here are some examples: 1. Imm = 0x000000007fff0000 LUi $dst, 7ffff // load immediate to upper 16-bit 2. Imm = 0x000000007fffffff LUi $r0, 7ffff ORi $dst, $r0, fffff 3. Imm = 0x00000fffffffffff ADDiu $r0, $zero, 1 SLL $r1, $r0, 44 // 44-bit shift left logical ADDiu $dst, $r1, fffff // add -1. the imm operand 0xffff is sign-extended to 64-bit when added. Currently, I have the following patterns (the last instruction of the sequence, or the root of the DAG, can be ADDiu, ORi, SLL or LUi): def...
2013 Feb 04
0
[LLVMdev] Problem with PTX assembly printing (NVPTX backend)
...# @main > .ent main > main: > .frame $sp,24,$ra > .mask 0x80000000,-4 > .fmask 0x00000000,0 > .set noreorder > .set nomacro > .set noat > # BB#0: > lui $2, %hi(_gp_disp) > addiu $2, $2, %lo(_gp_disp) > addiu $sp, $sp, -24 > sw $ra, 20($sp) # 4-byte Folded Spill > addu $gp, $2, $25 > lw $1, %got($str)($gp) > lw $25, %call16(puts)($gp) > jalr $25 > addiu $4, $1,...
2011 Oct 05
4
[LLVMdev] MIPS 32bit code generation
Hi, In order to emit "la $4,ADDR" instead of lui followed by addiu to load the data address, could you advise what is proper way to revise td files in the MIPS target? Thanks, -- Gang-Ryung Uh, Associate Professor Department of Computer Science College of Engineering, Boise State Univerisity tel: 1 208 426-5691 e-mail:guh at boisestate.edu http://cs.boisestate...
2013 Aug 29
2
[LLVMdev] .globl
I need to be able to emit .globl for the soft float routines used by mips16. The routines are called but there is no .globl definition for them. How can I do this? Background: I have a strange issue that I encountered with mips16 hard float. Part of mips16 hard float is to emit calls to runtime routines with the same signature as usual soft float routines, except that they are implemented
2013 Oct 03
1
[LLVMdev] Help with a Microblaze code generation problem.
...ich works, of course) for both unsigned long long and signed long long with the following results: unsigned long long: main: .frame $fp,24,$ra .mask 0x40000000,-4 .fmask 0x00000000,0 .set noreorder .set nomacro .set noat addiu $sp, $sp, -24 sw $fp, 20($sp) move $fp, $sp sw $zero, 16($fp) addiu $1, $zero, 100 sw $1, 12($fp) sw $zero, 8($fp) lui $1, 32768 sw $1, 0($fp) sw $zero, 4($fp) lw...
2016 Nov 29
2
[LLD] Writing thunks before the corresponding section
...t. > > On Wed, Sep 7, 2016 at 6:58 AM, Simon Atanasyan <simon at atanasyan.com> wrote: >> >> Hi, >> >> MIPS LA25 thunk is used to call PIC function from non-PIC code. >> Usually it contains three instructions: >> >> lui $25, %hi(func) >> addiu $25, $25, %lo(func) >> j func >> >> We can write such thunk in an arbitrary place of the generated file. >> But if a PIC function requires the thunk is the first routine in a >> section, we can optimize the code and escape jump instruction. To do >> so we jus...
2016 Sep 07
5
[LLD] Writing thunks before the corresponding section
Hi, MIPS LA25 thunk is used to call PIC function from non-PIC code. Usually it contains three instructions: lui $25, %hi(func) addiu $25, $25, %lo(func) j func We can write such thunk in an arbitrary place of the generated file. But if a PIC function requires the thunk is the first routine in a section, we can optimize the code and escape jump instruction. To do so we just write the following thunk right before the PIC rout...