search for: addi

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2004 Sep 10
1
altivec lpc_restore_signal
...; I haven't yet run this through simg4, so there may be some avoidable stalls, ; and there may be a somewhat more clever way to do the outer loop ; the branch mechanism may prevent dynamic loading; I still need to examine ; this issue, and there may be a more elegant method stmw r31,-4(r1) addi r9,r1,-28 li r31,0xf andc r9,r9,r31 ; for quadword-aligned stack data slwi r6,r6,2 ; adjust for word size slwi r4,r4,2 add r4,r4,r8 ; r4 = data+data_len mfspr r0,256 ; cache old vrsave addis r31,0,hi16(0xfffffc00) ori r31,r31,lo16(0xfffffc00) mtspr 256,r31 ; declare VRs in vrsave cmplw...
2013 Apr 05
3
[LLVMdev] Generate addi 40, r3 instruction
I want to generate the instruction like addi 40, r3 ! i.e. r3 = r3 + 40 The format i wrote is def ADDI : F1<opcode, (outs IntRegs:$dst), (ins IntRegs:$dst, i32imm:$imm) "addi $imm, $dst", [(set $IntRegs:$dst, (add $IntRegs:$dst, i32imm:$c))] but it is not compiling. what s...
2019 Jul 11
2
Manipulating global address inside GlobalAddress SDNode in (RISCV) LLVM backend
> > I don't think there's a real shortage of those, but I confess I'm not > sure why that's related. You'd need a representation for the LUI and > ADDI after instruction selection anyway. Yeah at the end we need a representation for LUI and ADDI. We were trying to break the 64 bit address from GlobalAddress node into two i32 register. We will add custom load/store which will generate the address using values from two registers. We thought LUI an...
2004 Oct 06
3
flac-1.1.1 completely broken on linux/ppc and on macosx if built with the standard toolchain (not xcode)
...roke completely everything. The asm code isn't gas compliant. the libFLAC linker script has a typo, disabling the asm optimization and/or altivec won't let a correct build anyway. Instant fixes for the asm stuff: sed -i -e"s:;:\#:" on the lpc_asm.s to load address instead of addis+ori you could use lis and la and PLEASE use the @l(register) and @ha macros instead of the not gas supported hi/lo16(). eg: lis 31,LABEL@ha la 31,LABEL@l(31) append use -mregnames as as options (remove the other) (the option there isn't present in the as manual, and I could just try to...
2019 Jan 15
4
Aggressive optimization opportunity
..._args opt equals to: int foo(int * restrict a) Here is a complete example: source code: extern int num; int foo(int * a) { (*a) = 10; num++; (*a)++; return *a; } Using IBM xlc compiler with option -qrestrict at -O2, we get result: 0000000000000000 <foo>: 0: 00 00 4c 3c addis r2,r12,0 4: 00 00 42 38 addi r2,r2,0 8: 00 00 a2 3c addis r5,r2,0 c: 00 00 a5 e8 ld r5,0(r5) 10: 0b 00 00 38 li r0,11 14: 00 00 03 90 stw r0,0(r3) 18: 00 00 85 80 lwz r4,0(r5) 1c: 0b 00 60 38 li r3,11 ---...
2019 Jul 11
6
Glue to connect two nodes in LLVM backend
Hello everyone, I wanted to attach a node without affecting the present nodes in any way. I tried to use MVT::Glue for that but I think I'm missing something as I could not achieve the below state. LUI LUI | | ADDI ----GLUE---- ADDI | store I've few question about this and Glue node in general, I'll be happy to get some help on this :) 1. Is Gluing the right approach or there is something better for such use case? 2. If I do something like DAG.getNode(ISD::ADDI, DL, MVT::Glue, LUINode, OtherADDINod...
2020 Jan 30
2
RISC-V disassembly doesn't seem to know about multiply instructions
...bly of section .text: 00000000 .text: /usr/local/google/home/pkapsenb/work/llvm-project/build/bin/llvm-objdump: warning: 'main.o': failed to parse debug information for main.o 0: 01 00 nop 00000002 main: ; int main() { 2: 41 11 addi sp, sp, -16 4: 06 c6 sw ra, 12(sp) 6: 22 c4 sw s0, 8(sp) 8: 00 08 addi s0, sp, 16 a: 09 45 addi a0, zero, 2 ; uint8_t a = 2; c: a3 0b a4 fe...
2019 Jul 09
2
Manipulating global address inside GlobalAddress SDNode in (RISCV) LLVM backend
...say i64 = GlobalAddress<0xHighLow> we want to convert it into i32 = GlobalAddress<0xLow>. [The below part is in reference with the RISCV LLVM backend] If there is no direct way to do this, we plan to fall back on a backup plan to convert the GlobalAddress node into the required LUI and ADDI pair but that would require the addition of two new target flag in RISCVII namespace. - Reshabh -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190709/aa10043d/attachment.html>
2014 Nov 26
2
[LLVMdev] How to make correct pattern for instruction?
Hi, I'm a beginner user using LLVM, and I'm trying to create a new backend using CPU0 Tutorial as reference. I have two instructions for add: add and addi (this is a pseudo instruction, but imediate operations is not available in architecture). That is my idea: When the LLVM instruction selection find addi r3 = r2 + value must convert to this: - load r1, value - add r3 = r2 + r1 In archInstrInfo.td I declared the instructions of the architecture,...
2004 Jul 14
1
oh323 dial structure and oh323 debug?
According to the wiki at voip-info.org, the dial structure for using oh323 without a gatekeeper is: OH323/<exten>@<host>:<port> or OH323/<exten> The second option is valid only in the case where a gatekeeper is used. NOTE: OpenH323 library v1.12.0 has a bug in the parsing of the destination host. When this version is used then the above syntax should be:
2013 Apr 05
0
[LLVMdev] Generate addi 40, r3 instruction
Hi Vikram, The error message would be helpful, but the most likely problem is the duplication of $dst. It should probably be: def ADDI : F1<opcode, (outs IntRegs:$dst), (ins IntRegs:$src, i32imm:$imm) "addi $imm, $dst", [(set $IntRegs:$dst, (add $IntRegs:$src, i32imm:$c))]> { let Constraints = "$src = $dst"; } i.e. separate registers, but a constraint noting...
2014 Nov 27
2
[LLVMdev] How to make correct pattern for instruction?
...like add r1, r0, -40). Cheers, Carlos Carlos Almeida Jr On Thu, Nov 27, 2014 at 7:56 AM, Johnny Val <johnnydval at gmail.com> wrote: > Hi Carlos, > > LLVM will do this automatically for you! There is no need for a pseudo > instruction in this case. As long as you have a way of adding two i32s (or > any other type) using registers then LLVM will automatically do what you > described when immediates are involved. > > Cheers, > > Johnny > > On Wed, Nov 26, 2014 at 11:50 PM, Carlos Almeida Jr. <almeidajr at gmail.com> > wrote: > >> Hi, &g...
2015 Nov 21
2
[lld] R_MIPS_HI16 / R_MIPS_LO16 calculation
...BI authors did mean by the "R_MIPS_HI16 must have an associated R_MIPS_LO16 entry immediately following it" phrase. In fact you can get from a compiler this code: lui $t0,%hi(sym1+4) # R_MIPS_HI16 lui $t0,%hi(sym1+8) # R_MIPS_HI16 lui $t0,%hi(sym1+12) # R_MIPS_HI16 addi $t0,$t0,%lo(sym1+16) # R_MIPS_LO16 and even such code: lui $t0,%hi(sym1) # R_MIPS_HI16 on sym1 lui $t0,%hi(sym2) # R_MIPS_HI16 on sym2 addi $t0,$t0,%lo(sym1) # R_MIPS_LO16 on sym1 addi $t0,$t0,%lo(sym2) # R_MIPS_LO16 on sym2 fortunately I have never seen such code: lui $t...
2010 Oct 04
2
[LLVMdev] missing blocks
.... Anyone have any idea what I may have done wrong? .file "/tmp/20000112-1.bc" .text .globl main .align 4 .type main, at function main: # @main # BB#0: # %entry addi %r1, %r1, -32 st %r31, %r1,28 st %r12, %r1,24 addi %r12, %r0, 0 st %r12, %r1,20 addi %r2, %r0, 1 call special_format oris r0,r0,0 subc r0, %r2, %r12 beq .LBB0_2 oris r0,r0,0 b .LBB0_1 oris r0...
2017 Jul 11
8
[LLD] Linker Relaxation
...board): #include <stdio.h> int foo(int i){ if (i < 100){ printf("%d\n", i); } return i; } int main(){ foo(10); return 0; } After compiling to a .o with -O2 -march=RV32IC we get (just looking at foo) 00000000 <foo>: 0: 1141 addi sp,sp,-16 2: c422 sw s0,8(sp) 4: c606 sw ra,12(sp) 6: 06300793 li a5,99 a: 842a mv s0,a0 c: 00a7cb63 blt a5,a0,22 <.L2> 10: 85aa mv a1,a0 12: 00000537 lui a0,0x0 16: 00050513...
2010 May 11
1
clients obtaining dhcp addys slowly
Hi all, This is unusual for me to observe. I've a dhcp server running on Centos 5.3 and it takes a while to answer clients asking for an address. This is playing some havoc with certain scripts at startup not fully working because of the address delay. I've even used a dhcp helper address type function in my Juniper router but nothing has changed. Any ideas?
2003 Aug 19
0
Joining samba-2.2.x to a domain.
...9;FOO') and samba-2.2.7a as a fileserver (netbiosname 'HAILSTORM') on the same machine. (different interfaces) The PDC is all set up and I've joined several windows 2000 clients and I encounterd no real problems. But all the files on the samba-2.2.a server are owned by HAILSTORM\addi but not FOO\addi titanium /etc/samba# smbpasswd -U root -r 10.0.0.1 -j FOO Password: Joined domain FOO. titanium /etc/samba# smbclient //hailstorm/sameign -U addi added interface ip=10.0.0.55 bcast=10.0.0.255 nmask=255.255.255.0 Password: Domain=[FOO] OS=[Unix] Server=[Samba 2.2.7a-security-roll...
2017 Jul 11
4
[LLD] Linker Relaxation
...>> return i; >> } >> >> int main(){ >> foo(10); >> return 0; >> } >> >> After compiling to a .o with -O2 -march=RV32IC we get (just looking at >> foo) >> >> 00000000 <foo>: >> 0: 1141 addi sp,sp,-16 >> 2: c422 sw s0,8(sp) >> 4: c606 sw ra,12(sp) >> 6: 06300793 li a5,99 >> a: 842a mv s0,a0 >> c: 00a7cb63 blt a5,a0,22 <.L2> >> 10: 85aa mv a1,a0...
2005 Apr 06
0
Bug? Authentication failure with multiple logins from same client IP addy
...still see failures with 20 concurrent connections from the same client IP. I believe that this problem is related to the fact that each of these connections is logging in separately instead of using a shared authentication... QUESITON: Are there any other paramters that we should change to allow additional authentications to succeed?...if not, is this a bug that I should report to the SAMBA team? or is this a known bug? (I've not seen this specific problem referenced) This problem is driving us crazy! Help! -David *-Attachment--- log.smbd [2005/04/05 04:39:22, 2] auth/auth.c:check_ntlm...
2013 Jul 09
1
[LLVMdev] Optimization issue for target's offset field of load operation in DAGSelection
I am working on an experimental target and trying to make sure that the load offset field is used to the best way. There appears to be some control over the architecture's offset range and whether the offset is too large and needs to be lowered/converted into a separate sequence of operations in DAGSelection? Can someone point me to what might be the case? For example, the difference between