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Hi All. I'm writing storeRegToStackSlot and loadFromStackSlot function for my Target. This Target can store/load one byte (not all word) from FrameIndex. If I need to store 16 bit register I will must to split it to two instruction like this: BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(0) .addReg(SrcReg, 0, Z80::subreg_lo); BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) .addFrameIndex(FrameIndex).addImm(1) .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); After this store I catch assertion failed: "Instruction not found in maps", because on...

...ting storeRegToStackSlot and loadFromStackSlot function for my > Target. This Target can store/load one byte (not all word) from FrameIndex. > If I need to store 16 bit register I will must to split it to two > instruction like this: > > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).**addImm(0) > .addReg(SrcReg, 0, Z80::subreg_lo); > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).**addImm(1) > .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); > > After this store I catch assertion failed: "Instruction not fo...

...Slot and loadFromStackSlot function for > my Target. This Target can store/load one byte (not all word) from > FrameIndex. If I need to store 16 bit register I will must to > split it to two instruction like this: > > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).addImm(0) > .addReg(SrcReg, 0, Z80::subreg_lo); > BuildMI(MBB, MI, dl, get(Z80::LD8xmr)) > .addFrameIndex(FrameIndex).addImm(1) > .addReg(SrcReg, getKillRegState(isKill), Z80::subreg_hi); > > After this store I catch assertion failed: "In...

...9;t getting set for the first > instruction there. yes, this needs to be added for each target. for our target i've modified the loadRegFromStackSlot and storeRegToStackSlot methods to add information on the frame index: BuildMI(MB, MBI, TII.get(STORE_REG_IMM)).addReg(framePointer) .addFrameIndex(FrameIndex).addReg(SrcReg).addSVOp(FrameIndex); > I'm curious why you added a new node kind, TargetSrcValue, instead of just > using the existing SRCVALUE. this is needed to ensure that the lowering pass does not rewrite them. i don't know if this is actually done, but anyway i wan...

...MOStore, 0, MFI.getObjectSize(FrameIdx), MFI.getObjectAlignment(FrameIdx)); unsigned tmpVReg = MF.getRegInfo().createVirtualRegister(OURTARGET::IntRegsRegisterClass); MachineInstr* mi = BuildMI(MBB, MI, DL, get(OURTARGET::ADDri), tmpVReg).addFrameIndex(FrameIdx).addImm(0); BuildMI(MBB, MI, DL, get(OURTARGET::STORE)).addReg(tmpVReg).addReg(SrcReg).addMemOperand(MMO); } Thanks a lot! Per -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110125/72f21fed/attac...

On Mon, Jul 23, 2007 at 02:19:38PM +0200, Florian Brandner wrote: > hi, > > i know it took a while, but here is a patch that adds a list of source > values to machine instructions. Cool! > i've testet all this for our backend only, which is not public. i do not > know how much has to be done to integrate this with the other, e.g., the > x86, targets. does any of the

Hi,   For a custom target, there is a pass to perform memory dependence analysis, where, i need to get memory pointer for "load instruction". I want to check the pointer alias behavior. I am getting this by considering the memoperands for the load instruction.   For "load instruction", Machine Instruction dumps as below:   vr12<def> = LD_Iri %vr2<kill>, 0;

hi, i know it took a while, but here is a patch that adds a list of source values to machine instructions. i modified the DAGISelEmiter to automatically catch regular loads/stores. custom instructions and loads/stores rewritten by the lowering pass are not automatically captured. during the instruction selection a source value operand is added to the DAG for patterns matching a load/store.