Displaying 12 results from an estimated 12 matches for "8da5051".
2016 Oct 27
1
[PATCH v2 6/7] copy: add maxwell/pascal copy engine classes
...= {
> + { 0xc0b5, 0, nouveau_copya0b5_init },
> + { 0xb0b5, 0, nouveau_copya0b5_init },
> { 0xa0b5, 0, nouveau_copya0b5_init },
> { 0x90b8, 5, nouveau_copy90b5_init },
> { 0x90b5, 4, nouveau_copy90b5_init },
> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
> index 8da5051..d0a835e 100644
> --- a/src/nvc0_accel.c
> +++ b/src/nvc0_accel.c
> @@ -156,9 +156,17 @@ NVAccelInitCOPY_NVE0(ScrnInfoPtr pScrn)
> {
> NVPtr pNv = NVPTR(pScrn);
> struct nouveau_pushbuf *push = pNv->pushbuf;
> + uint32_t class;
> int ret;
>
> - ret = nouveau_...
2016 Oct 27
2
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...++++++++++++++++++++++++++++++
> src/nvc0_exa.c | 23 ++++---------------
> src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
> 4 files changed, 93 insertions(+), 64 deletions(-)
>
> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
> index 0682806..8da5051 100644
> --- a/src/nvc0_accel.c
> +++ b/src/nvc0_accel.c
> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
> PUSH_DATA (push, (bo->offset + MISC_OFFSET));
> PUSH_DATA (push, 1);
> + } else {
&...
2016 Oct 16
0
[PATCH 5/5] recognize and accelerate GM20x
..., "Unknown chipset: NV%02X\n", chipset);
@@ -941,6 +942,7 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
pNv->Architecture = NV_KEPLER;
break;
case 0x110:
+ case 0x120:
pNv->Architecture = NV_MAXWELL;
break;
default:
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 8da5051..996fb88 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -236,9 +236,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
} else if (pNv->dev->chipset < 0x110) {
class = 0xa197;
handle = 0x0000906e;
- } else {
+ } else if (pNv->dev->chipset < 0x120) {
class = 0xb097;...
2016 Oct 17
2
[PATCH 5/5] recognize and accelerate GM20x
...> @@ -941,6 +942,7 @@ NVPreInit(ScrnInfoPtr pScrn, int flags)
> pNv->Architecture = NV_KEPLER;
> break;
> case 0x110:
> + case 0x120:
> pNv->Architecture = NV_MAXWELL;
> break;
> default:
> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
> index 8da5051..996fb88 100644
> --- a/src/nvc0_accel.c
> +++ b/src/nvc0_accel.c
> @@ -236,9 +236,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
> } else if (pNv->dev->chipset < 0x110) {
> class = 0xa197;
> handle = 0x0000906e;
> - } else {
> + } else if (pNv->dev->chi...
2016 Oct 27
0
[PATCH v2 6/7] copy: add maxwell/pascal copy engine classes
...Bool (*init)(NVPtr);
} methods[] = {
+ { 0xc0b5, 0, nouveau_copya0b5_init },
+ { 0xb0b5, 0, nouveau_copya0b5_init },
{ 0xa0b5, 0, nouveau_copya0b5_init },
{ 0x90b8, 5, nouveau_copy90b5_init },
{ 0x90b5, 4, nouveau_copy90b5_init },
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 8da5051..d0a835e 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -156,9 +156,17 @@ NVAccelInitCOPY_NVE0(ScrnInfoPtr pScrn)
{
NVPtr pNv = NVPTR(pScrn);
struct nouveau_pushbuf *push = pNv->pushbuf;
+ uint32_t class;
int ret;
- ret = nouveau_object_new(pNv->channel, 0x0000a0b5, 0xa0b5,...
2016 Oct 17
2
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...++++++++++++++++++++++++++++++
> src/nvc0_exa.c | 22 ++++---------------
> src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
> 4 files changed, 93 insertions(+), 63 deletions(-)
>
> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
> index 0682806..8da5051 100644
> --- a/src/nvc0_accel.c
> +++ b/src/nvc0_accel.c
> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
> PUSH_DATA (push, (bo->offset + MISC_OFFSET));
> PUSH_DATA (push, 1);
> + } else {
&...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...t;> src/nvc0_exa.c | 23 ++++---------------
>> src/nvc0_xv.c | 67
>> +++++++++++++++++++-------------------------------------
>> 4 files changed, 93 insertions(+), 64 deletions(-)
>>
>> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
>> index 0682806..8da5051 100644
>> --- a/src/nvc0_accel.c
>> +++ b/src/nvc0_accel.c
>> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
>> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
>> PUSH_DATA (push, (bo->offset + MISC_OFFSET));...
2016 Oct 16
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
src/nvc0_exa.c | 22 ++++---------------
src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
4 files changed, 93 insertions(+), 63 deletions(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strict...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++
src/nvc0_exa.c | 23 ++++---------------
src/nvc0_xv.c | 67 +++++++++++++++++++-------------------------------------
4 files changed, 93 insertions(+), 64 deletions(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strict...
2016 Oct 17
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...t;> src/nvc0_exa.c | 22 ++++---------------
>> src/nvc0_xv.c | 67
>> +++++++++++++++++++-------------------------------------
>> 4 files changed, 93 insertions(+), 63 deletions(-)
>>
>> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
>> index 0682806..8da5051 100644
>> --- a/src/nvc0_accel.c
>> +++ b/src/nvc0_accel.c
>> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
>> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
>> PUSH_DATA (push, (bo->offset + MISC_OFFSET));...
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++----------------
2 files changed, 892 insertions(+), 340 deletions(-)
create mode 100644 src/hwdefs/gm107_texture.xml.h
diff --git
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update