search for: 0xc0000

Hi everyone, There are 16 GPRs in my RISC, but in fact GPR13 is read-only and connected to output of an A/D converter. It would be very convenient if i could bind a register variable with GPR13. Because i am a newbie i don't know how my llvm backend can support that. I plan to implement it as below. A. first declare a global variable in c-code int ADC asm("GPR13"); B. If

...uld >>> * happen >>> */ >>> if (mas_walk(&mas)) >>> return -EEXIST; >>> >> >> For some reason mas_walk() finds an entry and hence this function returns >> -EEXIST for the following sequence of insertions. >> >> A = [0xc0000 - 0xfffff] >> B = [0x0 - 0xbffff] >> >> Interestingly, inserting B before A works fine. >> >> I attached a test module that reproduces the issue. I hope its just a stupid >> mistake I just can't spot though. > > This is probably my fault in how I expla...

.../* wait for ltssm idle */ > + nvkm_msec(device, 200, > + if ((nvkm_rd32(device, 0x8c040) & 0x1f) == 0) > + break; > + ); What if it doesn't idle? Should you still do the below things? > nvkm_mask(device, 0x8c040, 0xc0000, mask_value); > nvkm_mask(device, 0x8c040, 0x1, 0x1); > } > -- > 2.21.0 > > _______________________________________________ > Nouveau mailing list > Nouveau at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/nouveau

...ind a register variable with a given general purpose register? > > hi zhu, > > i think you should map the peripheral registers to data memory space > instead of register file, then mark that memory address as "volatile". > like said the adc register was mapped to address 0xc0000, and then the > corresponding c source will goes like this: > //define the register > #define ADCREG (*((volatile unsigned int *)0xc0000)) > //read the register > a = ADCREG > > --ether > > On 2010-1-4 10:59, Heyu Zhu wrote: > >> Hi everyone, >> There ar...

...with a given general purpose register? >> >> hi zhu, >> >> i think you should map the peripheral registers to data memory space >> instead of register file, then mark that memory address as "volatile". >> like said the adc register was mapped to address 0xc0000, and then the >> corresponding c source will goes like this: >> //define the register >> #define ADCREG (*((volatile unsigned int *)0xc0000)) >> //read the register >> a = ADCREG >> >> --ether >> >> On 2010-1-4 10:59, Heyu Zhu wrote: >> &g...

...ements a new mechanism to buffer the MMIO_WRITE and PIO_WRITE packet in a queue, and then submit them to qemu-dm in batch. This could save a lot of domain switch time. We implement this as a generic one to do ioreq in batch. However, we only use it to batch the MMIO_WIRTE request for stdvga(0xA0000-0xC0000) in order to solve the win2k boot issue for hvm domain. Without this patch, win2k cannot boot up on HVM domain. Signed-off-by: Zhu Han <zhu.han@intel.com> Signed-off-by: Eddie Dong <eddie.dong@intel.com> Signed-off-by: Xin Li <xin.b.li@intel.com> Best Regards, hanzhu ______...

...nknown card> (vendor=0x11d4, dev=0x1805) at 13.0 irq 15 isab0: <PCI to EISA bridge (vendor=0e11 device=0001)> at device 20.0 on pci0 eisa0: <EISA bus> on isab0 mainboard0: <CPQ0551 (System Board)> on eisa0 slot 0 isa0: <ISA bus> on isab0 orm0: <Option ROMs> at iomem 0xc0000-0xc7fff,0xe8000-0xedfff,0xee000-0xeffff on isa0 ep0: <3Com 3C509-Combo EtherLink III> at port 0x320-0x32f irq 10 on isa0 ep0: Ethernet address 00:a0:24:1d:1a:50 fdc0: <NEC 72065B or clone> at port 0x3f0-0x3f5,0x3f7 irq 6 drq 2 on isa0 fdc0: FIFO enabled, 8 bytes threshold fd0: <1440-...

..._supported(struct nvkm_pci *pci) { @@ -142,6 +144,11 @@ gk104_pcie_set_link_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed) break; } + /* wait for ltssm idle */ + nvkm_msec(device, 200, + if ((nvkm_rd32(device, 0x8c040) & 0x1f) == 0) + break; + ); nvkm_mask(device, 0x8c040, 0xc0000, mask_value); nvkm_mask(device, 0x8c040, 0x1, 0x1); } -- 2.21.0

...> --- 1.1/tools/ioemu/hw/pc.c 2005-05-19 15:04:52 -07:00 +++ edited/tools/ioemu/hw/pc.c 2005-05-23 16:37:18 -07:00 @@ -419,11 +419,11 @@ ret = load_image(buf, phys_ram_base + vga_bios_offset); #endif +#ifndef NOBIOS /* setup basic memory access */ cpu_register_physical_memory(0xc0000, 0x10000, vga_bios_offset | IO_MEM_ROM); -#ifndef NOBIOS /* map the last 128KB of the BIOS in ISA space */ isa_bios_size = bios_size; if (isa_bios_size > (128 * 1024)) ===== tools/ioemu/target-i386-dm/helper2.c 1.2 vs edited ===== --- 1.2/tools...

Attched please review the patch for hvm acpi dsdt table update: 1)Fixed HCT test "Unreported Memory and I/O Port test" for memory range 0xC0000~0xFFFFF and IO 0x378 2)Make consistent with non-acpi os by enabling LPT1, remove com2 which is conflict with usb mouse 3)Fixed the USB HID-Compliant mouse when set usbdevice=''tablet''/''mouse'' 4)Fixed Vista boot by removing old NIC "resourceConsumer" Sig...

...set the Asterisk to leave a video message to the mailbox, but there is some compatibility problem, although h263 is identified as the matching codec, as you can see in the debug messages below: Capabilities: us - 0x80100 (g729|h263), peer - audio=0x43f (g723|gsm|ulaw|alaw|g726|adpcm|ilbc)/video=0xc0000 (h261|h263), combined - 0x80000 (h263) Non-codec capabilities: us - 0x1 (telephone-event), peer - 0x1 (telephone-event), combined - 0x1 (telephone-event) ... ... Oct 29 16:20:58 WARNING[3098]: channel.c:506 ast_best_codec: Don't know any of 0x80000 formats Does anyone know how to resolve t...

...f irq 5 at device 4.0 on pci0 miibus0: <MII bus> on re0 rlphy0: <RealTek internal media interface> PHY 0 on miibus0 rlphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto re0: Ethernet address: 00:16:3e:00:00:03 re0: [FILTER] pmtimer0 on isa0 orm0: <ISA Option ROM> at iomem 0xc0000-0xc7fff pnpid ORM0000 on isa0 atkbdc0: <Keyboard controller (i8042)> at port 0x60,0x64 on isa0 atkbd0: <AT Keyboard> irq 1 on atkbdc0 kbd0 at atkbd0 atkbd0: [GIANT-LOCKED] atkbd0: [ITHREAD] psm0: <PS/2 Mouse> irq 12 on atkbdc0 psm0: [GIANT-LOCKED] psm0: [ITHREAD] psm0: model Intel...

everything was taken from nvgpu. Main reason for adding is to improve stability of the PCIe link changing code as we might want to depend on it for a workaround fixing our infamous runpm issues on recent laptops Karol Herbst (3): pci: force disable ASPM before changing the link speed pci/gk104: enable dl_mgr safe mode pci/gk104: wait for ltssm idle before changing the link

...ernet> port 0xec00-0xec1f mem 0xd8000000-0xd80fffff,0xd8100000-0xd8100fff irq 11 at device 8.0 on pci0 fxp0: Ethernet address 00:04:ac:a6:e7:3c inphy0: <i82555 10/100 media interface> on miibus0 inphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto orm0: <Option ROM> at iomem 0xc0000-0xcbfff on isa0 fdc0: <NEC 72065B or clone> at port 0x3f0-0x3f5,0x3f7 irq 6 drq 2 on isa0 atkbdc0: <Keyboard controller (i8042)> at port 0x60,0x64 on isa0 atkbd0: <AT Keyboard> flags 0x1 irq 1 on atkbdc0 kbd0 at atkbd0 vga0: <Generic ISA VGA> at port 0x3c0-0x3df iomem 0xa000...

...lTek 8029)> port 0x8000-0x801f irq 9 at device 17.0 on pci0 ed0: address 00:00:e8:e6:91:3b, type NE2000 (16 bit) pci0: <S3 ViRGE DX/GX graphics accelerator> at 18.0 eisa0: <EISA bus> on motherboard eisa0: unknown card FP@0000 (0x1a000000) at slot 7 orm0: <Option ROM> at iomem 0xc0000-0xc7fff on isa0 fdc0: <NEC 72065B or clone> at port 0x3f0-0x3f5,0x3f7 irq 6 drq 2 on isa0 fdc0: FIFO enabled, 8 bytes threshold fd0: <1440-KB 3.5" drive> on fdc0 drive 0 atkbdc0: <Keyboard controller (i8042)> at port 0x60,0x64 on isa0 atkbd0: <AT Keyboard> flags 0x1 irq...

Hi, any one help? I have puzzled by the question of device''s MMIO areas. I know a MMIO operation of guest os handled by VMM as follow steps: 1: Qemu-dm does its initialization and presents virtual devices for guest os. 2: virtual bios executes PCI_setup, it will scan the pci bus and get configure space of all devices,then virtual bios allocation system resources(like port I/O range,MMIO

If you start to experience problems with ata devices, please direct your report this way. Thanks -lq

...B6635 3.0LE host to PCI bridge> on motherboard pci2: <PCI bus> on pcib1 pcib2: <ServerWorks host to PCI bridge> on motherboard pci3: <PCI bus> on pcib2 pcib3: <ServerWorks host to PCI bridge> on motherboard pci4: <PCI bus> on pcib3 orm0: <Option ROMs> at iomem 0xc0000-0xc7fff,0xc8000-0xc8fff,0xc9000-0xcefff,0xcf000-0xcffff on isa0 fdc0: <NEC 72065B or clone> at port 0x3f0-0x3f5,0x3f7 irq 6 drq 2 on isa0 fdc0: FIFO enabled, 8 bytes threshold fd0: <1440-KB 3.5" drive> on fdc0 drive 0 atkbdc0: <Keyboard controller (i8042)> at port 0x60,0x64 o...

...0x3f0-0x3f5,0x3f7 irq 6 drq 2 on acpi0 fdc0: [FILTER] sio0: <16550A-compatible COM port> port 0x3f8-0x3ff irq 4 flags 0x10 on acpi0 sio0: type 16550A sio0: [FILTER] cpu0: <ACPI CPU> on acpi0 powernow0: <PowerNow! K7> on cpu0 pmtimer0 on isa0 orm0: <ISA Option ROMs> at iomem 0xc0000-0xcefff,0xcf000-0xcf7ff,0xdb000-0xdbfff,0xdc000-0xdffff pnpid ORM0000 on isa0 ppc0: <Parallel port> at port 0x378-0x37f irq 7 on isa0 ppc0: SMC-like chipset (ECP/EPP/PS2/NIBBLE) in COMPATIBLE mode ppc0: FIFO with 16/16/16 bytes threshold ppbus0: <Parallel port bus> on ppc0 ppbus0: [ITHR...

...l0: Ethernet address: 00:50:da:19:cc:b4 miibus0: <MII bus> on xl0 xlphy0: <3Com internal media interface> on miibus0 xlphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto chip0: <AcerLabs M15x3 Power Management Unit> at device 17.0 on pci0 orm0: <Option ROM> at iomem 0xc0000-0xcffff on isa0 fdc0: cannot reserve interrupt line atkbdc0: <Keyboard controller (i8042)> at port 0x60,0x64 on isa0 atkbd0: <AT Keyboard> flags 0x1 irq 1 on atkbdc0 kbd0 at atkbd0 vga0: <Generic ISA VGA> at port 0x3c0-0x3df iomem 0xa0000-0xbffff on isa0 sc0: <System console&gt...