Displaying 3 results from an estimated 3 matches for "0b001110".
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0b001100
2010 Jan 01
2
[LLVMdev] Assembly Printer
...ion is about pattern matching of instructions.
I found that some of the target instructions do not have corresponding
patterns to match.
For example, in SparcInstrInfo.td, "udiv" and "sdiv" don't seem to have any
patterns specified.
defm UDIV : F3_12np<"udiv", 0b001110>;
defm SDIV : F3_12np<"sdiv", 0b001111>;
Is this because these instructions are handled differently from other
instructions in SparcISelDAGToDAG.cpp?
In function SparcDAGToDAGISel::Select(SDValue Op), instruction selection for
"sdiv" and "udiv" is done in the...
2010 Jan 03
0
[LLVMdev] Assembly Printer
...tching of instructions.
> I found that some of the target instructions do not have corresponding patterns to match.
> For example, in SparcInstrInfo.td, "udiv" and "sdiv" don't seem to have any patterns specified.
>
> defm UDIV : F3_12np<"udiv", 0b001110>;
> defm SDIV : F3_12np<"sdiv", 0b001111>;
>
> Is this because these instructions are handled differently from other instructions in SparcISelDAGToDAG.cpp?
> In function SparcDAGToDAGISel::Select(SDValue Op), instruction selection for "sdiv" and "udiv&...
2011 Jul 03
0
[LLVMdev] DLX backend
...efm SUB : RegisterImmediateFormat<"sub", 0b001010, sub>;
// logical instructions
defm AND : RegisterImmediateFormat<"and", 0b001100, and>;
defm OR : RegisterImmediateFormat<"or", 0b001101, or>;
defm XOR : RegisterImmediateFormat<"xor", 0b001110, xor>;
// conditional instructions
/* ??? whats the format for the SDNode I need?
defm SEQ : RegisterImmediateFormat<"seq", 0b011000, icmp eq i32>;
defm SNE : RegisterImmediateFormat<"sne", 0b011001, icmp ne i32>;
defm SGE : RegisterImmediateFormat<"sge&q...