Displaying 4 results from an estimated 4 matches for "0b001100".
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2006 Oct 02
0
[LLVMdev] Instruction descriptions question
...1, sra>;
defm ADD : F3_12<"add" , 0b000000, add>;
defm ADDCC : F3_12<"addcc", 0b010000, addc>;
defm ADDX : F3_12<"addx" , 0b001000, adde>;
defm SUB : F3_12<"sub" , 0b000100, sub>;
defm SUBX : F3_12<"subx" , 0b001100, sube>;
defm SUBCC : F3_12<"subcc", 0b010100, SPcmpicc>;
...
Each of these 'defm's expand into two instructions.
> The semantic of such a description would mean that $dst should be one
> of GR8, GR16, GR32 and $dst is one of i8mem, i16mem, i32mem with the
> ad...
2006 Oct 01
2
[LLVMdev] Instruction descriptions question
Hi,
I'm trying to implement a new backend for an embedded CISC processor.
Therefore I thought that it makes sense to take X86 target as a basis,
to save some time.
But when I look into the X86InstrInfo.td, I have a very strong feeling
that it is one of the most complex instruction set descriptions
compared to other targets. I can imagine that this is due to the
complexity of X86's
2011 Jul 03
0
[LLVMdev] DLX backend
...m DIV : RegisterImmediateFormat<"div", 0b001001, udiv>;
defm MUL : RegisterImmediateFormat<"mul", 0b001011, mul>;
defm SUB : RegisterImmediateFormat<"sub", 0b001010, sub>;
// logical instructions
defm AND : RegisterImmediateFormat<"and", 0b001100, and>;
defm OR : RegisterImmediateFormat<"or", 0b001101, or>;
defm XOR : RegisterImmediateFormat<"xor", 0b001110, xor>;
// conditional instructions
/* ??? whats the format for the SDNode I need?
defm SEQ : RegisterImmediateFormat<"seq", 0b011000, i...
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
...: F3_12<"add" , 0b000000, add>;
> defm ADDCC : F3_12<"addcc", 0b010000, addc>;
> defm ADDX : F3_12<"addx" , 0b001000, adde>;
> defm SUB : F3_12<"sub" , 0b000100, sub>;
> defm SUBX : F3_12<"subx" , 0b001100, sube>;
> defm SUBCC : F3_12<"subcc", 0b010100, SPcmpicc>;
> ...
>
> Each of these 'defm's expand into two instructions.
>
>> The semantic of such a description would mean that $dst should be
one
>> of GR8, GR16, GR32 and $dst is one of i8mem...