Nouveau - Sep 2018 - [PATCH 0/5] drm/nouveau: add basic HDMI 2.0 support

This is the beginnings of HDMI 2.0 support. All of the "extra"
features are left out, such as 12/16bpc, YUV420, etc.

I've verified that with this code, a GP108 (GT1030) can switch between
4k at 60 and 1920x1080 at 60 on a LG 4K TV. Further, I've verified via i2c
tools, that the SCDC writes really do happen.

I suspect that the patch for keeping track of the high-speed TMDS
setting is somehow off, esp if one were to switch between HDMI and DVI
on the same port, or DP and HDMI. I'm quite confused about OR's vs
HEAD's, and how to tell whether a register is indexed by one or the
other. But at least it works a little bit!

Note that I have limited testing equipment, but I did verify that a
GM204 trace referred to the same register for controlling
scrambling. I may get access to a GM206 later in the week to verify
there.

Ilia Mirkin (5):
  drm/nouveau/disp: add a way to configure scrambling/tmds for hdmi 2.0
  drm/nouveau/disp/gm200-: add scdc parameter setter
  drm/nouveau/disp: keep track of high-speed state, program into clock
  drm/nouveau/disp: add support for setting scdc parameters for high
    modes
  drm/nouveau/disp: take sink support into account for exposing 594mhz

 drivers/gpu/drm/nouveau/dispnv50/disp.c            | 40 +++++++++++++++++++++-
 drivers/gpu/drm/nouveau/include/nvif/cl5070.h      |  5 ++-
 drivers/gpu/drm/nouveau/nouveau_connector.c        | 34 +++++++++++-------
 drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild    |  1 +
 .../gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c   | 36 +++++++++++++++++++
 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h     |  8 +++++
 .../gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c    | 10 ++++--
 .../gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c    | 11 +++---
 .../gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c    |  1 +
 .../gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c    |  1 +
 10 files changed, 127 insertions(+), 20 deletions(-)
 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c

-- 
2.16.4

High pixel clocks are required to use a 40 TMDS divider instead of 10,
and even low ones may optionally use scrambling depending on device
support.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
 drivers/gpu/drm/nouveau/include/nvif/cl5070.h       |  5 ++++-
 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h      |  1 +
 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c | 10 ++++++++--
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h
b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h
index 7cdf53615d7b..bced81987269 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h
@@ -69,7 +69,10 @@ struct nv50_disp_sor_hdmi_pwr_v0 {
 	__u8  rekey;
 	__u8  avi_infoframe_length;
 	__u8  vendor_infoframe_length;
-	__u8  pad06[2];
+#define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE (1 << 0)
+#define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 (1 << 1)
+	__u8  scdc;
+	__u8  pad07[1];
 };
 
 struct nv50_disp_sor_lvds_script_v0 {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
index e0b4e0c5704e..57ffadc6a38e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
@@ -60,6 +60,7 @@ struct nvkm_ior_func {
 		void (*ctrl)(struct nvkm_ior *, int head, bool enable,
 			     u8 max_ac_packet, u8 rekey, u8 *avi, u8 avi_size,
 			     u8 *vendor, u8 vendor_size);
+		void (*scdc)(struct nvkm_ior *, int head, u8 scdc);
 	} hdmi;
 
 	struct {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
index 3aa5a2879239..5f758948d6e1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
@@ -176,9 +176,10 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd,
void *data, u32 size)
 		nvif_ioctl(object, "disp sor hdmi ctrl size %d\n", size);
 		if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true)))
{
 			nvif_ioctl(object, "disp sor hdmi ctrl vers %d state %d "
-					   "max_ac_packet %d rekey %d\n",
+					   "max_ac_packet %d rekey %d scdc %d\n",
 				   args->v0.version, args->v0.state,
-				   args->v0.max_ac_packet, args->v0.rekey);
+				   args->v0.max_ac_packet, args->v0.rekey,
+				   args->v0.scdc);
 			if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f)
 				return -EINVAL;
 			if ((args->v0.avi_infoframe_length
@@ -202,6 +203,11 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd,
void *data, u32 size)
 					   args->v0.max_ac_packet,
 					   args->v0.rekey, avi, avi_size,
 					   vendor, vendor_size);
+
+		if (outp->ior->func->hdmi.scdc)
+			outp->ior->func->hdmi.scdc(
+					outp->ior, hidx, args->v0.scdc);
+
 		return 0;
 	}
 		break;
-- 
2.16.4

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
 drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild    |  1 +
 .../gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c   | 34 ++++++++++++++++++++++
 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h     |  2 ++
 .../gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c    |  1 +
 .../gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c    |  1 +
 5 files changed, 39 insertions(+)
 create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
index 3d485dbf310a..8089ac9a12e2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild
@@ -50,6 +50,7 @@ nvkm-y += nvkm/engine/disp/hdmig84.o
 nvkm-y += nvkm/engine/disp/hdmigt215.o
 nvkm-y += nvkm/engine/disp/hdmigf119.o
 nvkm-y += nvkm/engine/disp/hdmigk104.o
+nvkm-y += nvkm/engine/disp/hdmigm200.o
 nvkm-y += nvkm/engine/disp/hdmigv100.o
 
 nvkm-y += nvkm/engine/disp/conn.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
new file mode 100644
index 000000000000..ad5f658c3f6d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2018 Ilia Mirkin
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
"Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ilia Mirkin
+ */
+#include "hdmi.h"
+
+void
+gm200_hdmi_scdc(struct nvkm_ior *ior, int head, u8 scdc)
+{
+	struct nvkm_device *device = ior->disp->engine.subdev.device;
+	const u32 hoff = head * 0x800;
+	const u32 ctrl = scdc & 0x3;
+
+	nvkm_mask(device, 0x61c5bc + hoff, 0x00000003, ctrl);
+}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
index 57ffadc6a38e..cf640141ad23 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
@@ -144,6 +144,8 @@ void gf119_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8,
u8 *, u8 , u8 *, u8);
 void gk104_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *,
u8);
 void gv100_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *,
u8);
 
+void gm200_hdmi_scdc(struct nvkm_ior *, int, u8);
+
 void gt215_hda_hpd(struct nvkm_ior *, int, bool);
 void gt215_hda_eld(struct nvkm_ior *, u8 *, u8);
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
index d892bdf04034..384f82652bec 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
@@ -99,6 +99,7 @@ gm200_sor = {
 	.clock = gf119_sor_clock,
 	.hdmi = {
 		.ctrl = gk104_hdmi_ctrl,
+		.scdc = gm200_hdmi_scdc,
 	},
 	.dp = {
 		.lanes = { 0, 1, 2, 3 },
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c
b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c
index 040db8a338de..8ba881a729ee 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c
@@ -88,6 +88,7 @@ gv100_sor = {
 	.clock = gf119_sor_clock,
 	.hdmi = {
 		.ctrl = gv100_hdmi_ctrl,
+		.scdc = gm200_hdmi_scdc,
 	},
 	.dp = {
 		.lanes = { 0, 1, 2, 3 },
-- 
2.16.4

The register programmed by the clock method needs to contain a different
setting for the link speed as well as special divider settings.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c |  2 ++
 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h       |  5 +++++
 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c  | 11 +++++++----
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
index ad5f658c3f6d..9b16a08eb4d9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
@@ -31,4 +31,6 @@ gm200_hdmi_scdc(struct nvkm_ior *ior, int head, u8 scdc)
 	const u32 ctrl = scdc & 0x3;
 
 	nvkm_mask(device, 0x61c5bc + hoff, 0x00000003, ctrl);
+
+	ior->tmds.high_speed = !!(scdc & 0x2);
 }
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
index cf640141ad23..e2e0515a178c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
@@ -40,6 +40,11 @@ struct nvkm_ior {
 		u8 nr;
 		u8 bw;
 	} dp;
+
+	/* Armed TMDS state. */
+	struct {
+		bool high_speed;
+	} tmds;
 };
 
 struct nvkm_ior_func {
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
index e6e6dfbb1283..456a5a143522 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
@@ -120,13 +120,16 @@ void
 gf119_sor_clock(struct nvkm_ior *sor)
 {
 	struct nvkm_device *device = sor->disp->engine.subdev.device;
-	const int  div = sor->asy.link == 3;
 	const u32 soff = nv50_ior_base(sor);
+	u32 div1 = sor->asy.link == 3;
+	u32 div2 = sor->asy.link == 3;
 	if (sor->asy.proto == TMDS) {
-		/* NFI why, but this sets DP_LINK_BW_2_7 when using TMDS. */
-		nvkm_mask(device, 0x612300 + soff, 0x007c0000, 0x0a << 18);
+		const u32 speed = sor->tmds.high_speed ? 0x14 : 0x0a;
+		nvkm_mask(device, 0x612300 + soff, 0x007c0000, speed << 18);
+		if (sor->tmds.high_speed)
+			div2 = 1;
 	}
-	nvkm_mask(device, 0x612300 + soff, 0x00000707, (div << 8) | div);
+	nvkm_mask(device, 0x612300 + soff, 0x00000707, (div2 << 8) | div1);
 }
 
 void
-- 
2.16.4

When SCDC is supported, make sure that we configure the GPU and monitor
to the same parameters.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
 drivers/gpu/drm/nouveau/dispnv50/disp.c | 40 ++++++++++++++++++++++++++++++++-
 1 file changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 9bae4db84cfb..77cf5878896e 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -36,6 +36,7 @@
 #include <drm/drm_dp_helper.h>
 #include <drm/drm_fb_helper.h>
 #include <drm/drm_plane_helper.h>
+#include <drm/drm_scdc_helper.h>
 #include <drm/drm_edid.h>
 
 #include <nvif/class.h>
@@ -506,6 +507,7 @@ nv50_hdmi_disable(struct drm_encoder *encoder, struct
nouveau_crtc *nv_crtc)
 static void
 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
 {
+	struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 	struct nv50_disp *disp = nv50_disp(encoder->dev);
@@ -523,9 +525,12 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct
drm_display_mode *mode)
 		.pwr.rekey = 56, /* binary driver, and tegra, constant */
 	};
 	struct nouveau_connector *nv_connector;
+	struct drm_hdmi_info *hdmi;
 	u32 max_ac_packet;
 	union hdmi_infoframe avi_frame;
 	union hdmi_infoframe vendor_frame;
+	bool scdc_supported, high_tmds_clock_ratio = false, scrambling = false;
+	u8 config;
 	int ret;
 	int size;
 
@@ -533,8 +538,11 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct
drm_display_mode *mode)
 	if (!drm_detect_hdmi_monitor(nv_connector->edid))
 		return;
 
+	hdmi = &nv_connector->base.display_info.hdmi;
+	scdc_supported = hdmi->scdc.supported;
+
 	ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode,
-						       false);
+						       scdc_supported);
 	if (!ret) {
 		/* We have an AVI InfoFrame, populate it to the display */
 		args.pwr.avi_infoframe_length
@@ -557,12 +565,42 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct
drm_display_mode *mode)
 	max_ac_packet -= 18; /* constant from tegra */
 	args.pwr.max_ac_packet = max_ac_packet / 32;
 
+	if (hdmi->scdc.scrambling.supported) {
+		high_tmds_clock_ratio = mode->clock > 340000;
+		scrambling = high_tmds_clock_ratio ||
+			hdmi->scdc.scrambling.low_rates;
+	}
+
+	args.pwr.scdc +		NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
+		NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
+
 	size = sizeof(args.base)
 		+ sizeof(args.pwr)
 		+ args.pwr.avi_infoframe_length
 		+ args.pwr.vendor_infoframe_length;
 	nvif_mthd(&disp->disp->object, 0, &args, size);
+
 	nv50_audio_enable(encoder, mode);
+
+	/* If SCDC is supported by the downstream monitor, update
+	 * divider / scrambling settings to what we programmed above.
+	 */
+	if (!hdmi->scdc.scrambling.supported)
+		return;
+
+	ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
+	if (ret < 0) {
+		NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
+		return;
+	}
+	config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
+	config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
+	config |= SCDC_SCRAMBLING_ENABLE * scrambling;
+	ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
+	if (ret < 0)
+		NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
+			 config, ret);
 }
 
 /******************************************************************************
-- 
2.16.4

Scrambling is required for supporting any mode over 340MHz. If it's not
supported, reject any modes that would require it.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
 drivers/gpu/drm/nouveau/nouveau_connector.c | 34 +++++++++++++++++++----------
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c
b/drivers/gpu/drm/nouveau/nouveau_connector.c
index af68eae4c626..64228cc1412c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -977,18 +977,33 @@ nouveau_connector_get_modes(struct drm_connector
*connector)
 }
 
 static unsigned
-get_tmds_link_bandwidth(struct drm_connector *connector, bool hdmi)
+get_tmds_link_bandwidth(struct drm_connector *connector)
 {
 	struct nouveau_connector *nv_connector = nouveau_connector(connector);
+	struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
 	struct nouveau_drm *drm = nouveau_drm(connector->dev);
 	struct dcb_output *dcb = nv_connector->detected_encoder->dcb;
+	struct drm_display_info *info = NULL;
+	const unsigned duallink_scale +		nouveau_duallink &&
nv_encoder->dcb->duallink_possible ? 2 : 1;
+
+	if (drm_detect_hdmi_monitor(nv_connector->edid))
+		info = &nv_connector->base.display_info;
 
-	if (hdmi) {
+	if (info) {
 		if (nouveau_hdmimhz > 0)
 			return nouveau_hdmimhz * 1000;
 		/* Note: these limits are conservative, some Fermi's
 		 * can do 297 MHz. Unclear how this can be determined.
 		 */
+		if (drm->client.device.info.chipset >= 0x120) {
+			const int max_tmds_clock +				info->hdmi.scdc.scrambling.supported ?
+				594000 : 340000;
+			return info->max_tmds_clock ?
+				min(info->max_tmds_clock, max_tmds_clock) :
+				max_tmds_clock;
+		}
 		if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KEPLER)
 			return 297000;
 		if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
@@ -996,13 +1011,13 @@ get_tmds_link_bandwidth(struct drm_connector *connector,
bool hdmi)
 	}
 	if (dcb->location != DCB_LOC_ON_CHIP ||
 	    drm->client.device.info.chipset >= 0x46)
-		return 165000;
+		return 165000 * duallink_scale;
 	else if (drm->client.device.info.chipset >= 0x40)
-		return 155000;
+		return 155000 * duallink_scale;
 	else if (drm->client.device.info.chipset >= 0x18)
-		return 135000;
+		return 135000 * duallink_scale;
 	else
-		return 112000;
+		return 112000 * duallink_scale;
 }
 
 static enum drm_mode_status
@@ -1014,7 +1029,6 @@ nouveau_connector_mode_valid(struct drm_connector
*connector,
 	struct drm_encoder *encoder = to_drm_encoder(nv_encoder);
 	unsigned min_clock = 25000, max_clock = min_clock;
 	unsigned clock = mode->clock;
-	bool hdmi;
 
 	switch (nv_encoder->dcb->type) {
 	case DCB_OUTPUT_LVDS:
@@ -1027,11 +1041,7 @@ nouveau_connector_mode_valid(struct drm_connector
*connector,
 		max_clock = 400000;
 		break;
 	case DCB_OUTPUT_TMDS:
-		hdmi = drm_detect_hdmi_monitor(nv_connector->edid);
-		max_clock = get_tmds_link_bandwidth(connector, hdmi);
-		if (!hdmi && nouveau_duallink &&
-		    nv_encoder->dcb->duallink_possible)
-			max_clock *= 2;
+		max_clock = get_tmds_link_bandwidth(connector);
 		break;
 	case DCB_OUTPUT_ANALOG:
 		max_clock = nv_encoder->dcb->crtconf.maxfreq;
-- 
2.16.4

On Tue, 4 Sep 2018 at 10:59, Ilia Mirkin <imirkin at alum.mit.edu>
wrote:
>
> This is the beginnings of HDMI 2.0 support. All of the "extra"
> features are left out, such as 12/16bpc, YUV420, etc.
>
> I've verified that with this code, a GP108 (GT1030) can switch between
> 4k at 60 and 1920x1080 at 60 on a LG 4K TV. Further, I've verified via
i2c
> tools, that the SCDC writes really do happen.
>
> I suspect that the patch for keeping track of the high-speed TMDS
> setting is somehow off, esp if one were to switch between HDMI and DVI
> on the same port, or DP and HDMI. I'm quite confused about OR's vs
> HEAD's, and how to tell whether a register is indexed by one or the
> other. But at least it works a little bit!
I think the main thing you need to make that switching work is to
ensure the hdmi disable path reverts the scdc settings, which, I think
is already taken care of with your series.

HEAD is "CRTC", the thing that scans out the image from the FB.  OR is
the "output resource", responsible for encoding in the target display
protocol.  It's a bit confusing, because there's a bunch of HW that is
different between generations where certain things (like HDMI control,
for example) that used to be tied to the OR, but is now tied to the
HEAD.

Overall, I think the series looks fine so far.

Ben.
>
> Note that I have limited testing equipment, but I did verify that a
> GM204 trace referred to the same register for controlling
> scrambling. I may get access to a GM206 later in the week to verify
> there.
>
> Ilia Mirkin (5):
>   drm/nouveau/disp: add a way to configure scrambling/tmds for hdmi 2.0
>   drm/nouveau/disp/gm200-: add scdc parameter setter
>   drm/nouveau/disp: keep track of high-speed state, program into clock
>   drm/nouveau/disp: add support for setting scdc parameters for high
>     modes
>   drm/nouveau/disp: take sink support into account for exposing 594mhz
>
>  drivers/gpu/drm/nouveau/dispnv50/disp.c            | 40
+++++++++++++++++++++-
>  drivers/gpu/drm/nouveau/include/nvif/cl5070.h      |  5 ++-
>  drivers/gpu/drm/nouveau/nouveau_connector.c        | 34 +++++++++++-------
>  drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild    |  1 +
>  .../gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c   | 36
+++++++++++++++++++
>  drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h     |  8 +++++
>  .../gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c    | 10 ++++--
>  .../gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c    | 11 +++---
>  .../gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c    |  1 +
>  .../gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c    |  1 +
>  10 files changed, 127 insertions(+), 20 deletions(-)
>  create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c
>
> --
> 2.16.4
>
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