search for: scdc

This is the beginnings of HDMI 2.0 support. All of the "extra" features are left out, such as 12/16bpc, YUV420, etc. I've verified that with this code, a GP108 (GT1030) can switch between 4k at 60 and 1920x1080 at 60 on a LG 4K TV. Further, I've verified via i2c tools, that the SCDC writes really do happen. I suspect that the patch for keeping track of the high-speed TMDS setting is somehow off, esp if one were to switch between HDMI and DVI on the same port, or DP and HDMI. I'm quite confused about OR's vs HEAD's, and how to tell whether a register is indexed by...

I have a Gigabyte GeForce 1050 connected by DVI to a monitor (1920x1200 resolution @ 59.9502 Hz) and a TV via HDMI (3840x2160 @30 Hz). The problem is the TV used to work at 59.9685 Hz but then it started showing "No signal" on the TV. I was changing settings trying to get it to work again and I happened to change it to 30Hz and it worked. The specs are here:

...got 60Hz in the first place. In order for the high > rates to work, something called "scrambling" must be enabled. This is > done by 2-party agreement between the sink and the source. The sink > will inform the source that it's about to use scrambling (by writing > to the SCDC register on the display over i2c). > > In my personal experiments, on a LG C6 series TV, I found that while > EDID works while the TV is off, the SCDC write does not. So you can > actually "turn on" the display on the computer while the TV itself is > off, and the scrambli...

...d), which is why you got 60Hz in the first place. In order for the high rates to work, something called "scrambling" must be enabled. This is done by 2-party agreement between the sink and the source. The sink will inform the source that it's about to use scrambling (by writing to the SCDC register on the display over i2c). In my personal experiments, on a LG C6 series TV, I found that while EDID works while the TV is off, the SCDC write does not. So you can actually "turn on" the display on the computer while the TV itself is off, and the scrambling setting will not have...

...vers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c index 9b16a08eb4d9..bf6d41fb0c9f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c @@ -27,10 +27,10 @@ void gm200_hdmi_scdc(struct nvkm_ior *ior, int head, u8 scdc) { struct nvkm_device *device = ior->disp->engine.subdev.device; - const u32 hoff = head * 0x800; + const u32 soff = nv50_ior_base(ior); const u32 ctrl = scdc & 0x3; - nvkm_mask(device, 0x61c5bc + hoff, 0x00000003, ctrl); + nvkm_mask(device,...

...vers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c index 9b16a08eb4d9..bf6d41fb0c9f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c @@ -27,10 +27,10 @@ void gm200_hdmi_scdc(struct nvkm_ior *ior, int head, u8 scdc) { struct nvkm_device *device = ior->disp->engine.subdev.device; - const u32 hoff = head * 0x800; + const u32 soff = nv50_ior_base(ior); const u32 ctrl = scdc & 0x3; - nvkm_mask(device, 0x61c5bc + hoff, 0x00000003, ctrl); + nvkm_mask(device,...

Can you try something very simple - unplug the cable, and plug it back in, while the TV is on, and set to the HDMI input? That should ensure that the SCDC write can go through at modeset time. You can also force nouveau to avoid any modes that require scrambling by booting with nouveau.hdmimhz=340. Cheers, -ilia On Tue, Aug 6, 2019 at 1:15 PM James <bjlockie at lockie.ca> wrote: > > I was going to buy a new cable and I came across t...

...referred_mode); +static bool is_hdmi2_sink(struct drm_connector *connector) +{ + /* + * FIXME: sil-sii8620 doesn't have a connector around when + * we need one, so we have to be prepared for a NULL connector. + */ + if (!connector) + return true; + + return connector->display_info.hdmi.scdc.supported || + connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; +} + /** * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with * data from a DRM display mode * @frame: HDMI AVI infoframe + * @conn...

...: sil-sii8620 doesn't have a connector around when > + * we need one, so we have to be prepared for a NULL connector. > + */ > + if (!connector) > + return false; This actually changes the is_hdmi2_sink value for sil-sii8620. > + > + return connector->display_info.hdmi.scdc.supported || > + connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; > +} > + > /** > * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with > * data from a DRM display mode > * @...

...bject.h> #include <nvif/if0012.h> +#include <drm/display/drm_dp.h> struct nvif_disp; struct nvif_outp { @@ -21,7 +22,7 @@ int nvif_outp_acquire_rgb_crt(struct nvif_outp *); int nvif_outp_acquire_tmds(struct nvif_outp *, int head, bool hdmi, u8 max_ac_packet, u8 rekey, u8 scdc, bool hda); int nvif_outp_acquire_lvds(struct nvif_outp *, bool dual, bool bpc8); -int nvif_outp_acquire_dp(struct nvif_outp *, u8 dpcd[16], +int nvif_outp_acquire_dp(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], int link_nr, int link_bw, bool hda, bool mst); void nvif_outp_release(...

...m/display/drm_dp.h> > > struct nvif_disp; > > > > struct nvif_outp { > > @@ -21,7 +22,7 @@ int nvif_outp_acquire_rgb_crt(struct nvif_outp *); > > int nvif_outp_acquire_tmds(struct nvif_outp *, int head, > > bool hdmi, u8 max_ac_packet, u8 rekey, u8 scdc, bool hda); > > int nvif_outp_acquire_lvds(struct nvif_outp *, bool dual, bool bpc8); > > -int nvif_outp_acquire_dp(struct nvif_outp *, u8 dpcd[16], > > +int nvif_outp_acquire_dp(struct nvif_outp *outp, u8 dpcd[DP_RECEIVER_CAP_SIZE], > > int link_nr, int link_bw, bool...

...eferred_mode); +static bool is_hdmi2_sink(struct drm_connector *connector) +{ + /* + * FIXME: sil-sii8620 doesn't have a connector around when + * we need one, so we have to be prepared for a NULL connector. + */ + if (!connector) + return false; + + return connector->display_info.hdmi.scdc.supported || + connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; +} + /** * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with * data from a DRM display mode * @frame: HDMI AVI infoframe + * @conn...

...30Hz. I did just update the tv firmware s9 maybe that is why I can't get it 60Hz anymore. I wish I kept better track of the timeline. With the new HDMI 2 cable I get 4096x2160 at 30Hz (there is no 60Hz option). 3840x2160 at 59.9685Hz gives me no signal. > That should ensure > that the SCDC write can go through at modeset time. > > You can also force nouveau to avoid any modes that require scrambling > by booting with nouveau.hdmimhz=340. > > Cheers, > > -ilia > > On Tue, Aug 6, 2019 at 1:15 PM James <bjlockie at lockie.ca> wrote: >> >> I...

...50_hdmi_enable(struct drm_encoder *encoder, struct drm_atomic_state *state, + args.pwr.vendor_infoframe_length; nvif_mthd(&disp->disp->object, 0, &args, size); - nv50_audio_enable(encoder, state, mode); + nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); /* If SCDC is supported by the downstream monitor, update * divider / scrambling settings to what we programmed above. @@ -895,6 +908,7 @@ struct nv50_mstc { struct nv50_msto { struct drm_encoder encoder; + /* head is statically assigned on msto creation */ struct nv50_head *head; struct nv50_mstc...

...eturn; @@ -798,7 +849,7 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) + args.pwr.vendor_infoframe_length; nvif_mthd(&disp->disp->object, 0, &args, size); - nv50_audio_enable(encoder, mode); + nv50_audio_enable(encoder, state, mode); /* If SCDC is supported by the downstream monitor, update * divider / scrambling settings to what we programmed above. @@ -1573,7 +1624,8 @@ nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, } static void -nv50_sor_disable(struct drm_encoder *encoder) +nv50_sor_disable(struct drm_encoder *en...

To start off: this patch series is less work to review then it looks - most (but not all) of the nouveau related work has already been reviewed elsewhere. Most of the reason I'm asking for an RFC here is because this code pulls a lot of code out of i915 and into shared DP helpers. Anyway-nouveau's HPD related code has been collecting dust for a while. Other then the occasional runtime PM

Most of the reason I'm asking for an RFC here is because this code pulls a lot of code out of i915 and into shared DP helpers. Anyway-nouveau's HPD related code has been collecting dust for a while. Other then the occasional runtime PM related and MST related fixes, we're missing a lot of nice things that have been added to DRM since this was originally written. Additionally, the code

Most of the reason I'm asking for an RFC here is because this code pulls a lot of code out of i915 and into shared DP helpers. Anyway-nouveau's HPD related code has been collecting dust for a while. Other then the occasional runtime PM related and MST related fixes, we're missing a lot of nice things that have been added to DRM since this was originally written. Additionally, the code

To start off: this patch series is less work to review then it looks - most (but not all) of the nouveau related work has already been reviewed elsewhere. Most of the reason I'm asking for an RFC here is because this code pulls a lot of code out of i915 and into shared DP helpers. Anyway-nouveau's HPD related code has been collecting dust for a while. Other then the occasional runtime PM