similar to: inline assembly matching error

Displaying 20 results from an estimated 100 matches similar to: "inline assembly matching error"

2010 Jul 28
2
[LLVMdev] build errors while cross compiling llvm-gcc for ARM
Hello, I'm using gold linker now to see if there can be any performance gain. Also using latest gcc version (4.4.4) and latest binutils. But when I'm compiling llvm-gcc, I'm getting this error. /home/jal/llvm-gcc-4.2-2.7.source/host-i686-pc-linux-gnu/gcc/xgcc -B/home/jal/llvm-gcc-4.2-2.7.source/host-i686-pc-linux-gnu/gcc/ -B/usr/local/arm-v7a8-linux-gnueabi/bin/
2016 Jun 21
2
[LLD] thunk implementation correctness depends on order of input section.
I've been working on supporting ARM/Thumb interworking thunks in LLD and have encountered a limitation that I think it is worth bringing up in a wider context. This is all LLD specific, apologies if I've abused llvm-dev here. TL;DR summary: - Thunks in lld may not work if they are added to InputSections that have already been scanned. - There is a short term fix, but in the longer term I
2006 May 02
1
pairwise.t.test: empty p-table
Hi list-members can anybody tell me why > pairwise.t.test(val, fac) produces an empty p-table. As shown below: Pairwise comparisons using t tests with pooled SD data: val and fac AS AT Fhh Fm Fmk Fmu GBS Gf HFS Hn jAL Kol R_Fill AT - - - - - - - - - - - - - Fhh - - - - - - - - - - - - - Fm - - - - - - -
2013 Feb 27
2
[LLVMdev] Mips backend 3.2 va_arg possible bug
i have this code typedef long long L; typedef integer I; void test2(auto L p0, auto L p1, auto L p2, auto L p4, ...) { va_list select; va_start (select, p4); report( va_arg(select,L) ); report( va_arg(select,I) ); report( va_arg(select,L) );
2013 Feb 28
0
[LLVMdev] Mips backend 3.2 va_arg possible bug
Could you file a bug? On Wed, Feb 27, 2013 at 2:47 AM, Stavropoulos Nikos < n.stavropoulos at think-silicon.com> wrote: > i have this code > > typedef long long L; > typedef integer I; > void test2(auto L p0, auto L p1, auto L p2, auto L p4, ...) > { > va_list select; > > va_start (select, p4); > > report( va_arg(select,L) ); > report(
2019 Jan 18
0
[klibc:master] mips/mips64: simplify crt0 code
Commit-ID: 59f3f33338f371b3a30163406fbb5fe323503939 Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=59f3f33338f371b3a30163406fbb5fe323503939 Author: James Cowgill <james.cowgill at mips.com> AuthorDate: Fri, 2 Mar 2018 08:33:02 -0800 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Wed, 2 Jan 2019 03:08:04 +0000 [klibc] mips/mips64: simplify
2012 May 09
1
[LLVMdev] Directive parsing for AsmParser
I'm trying to build a standalone assembler for Mips using AsmParser and I'm facing a problem with assembly directives. Mips assembler has following syntax for .set directive .set reorder or .set noreorder which allow/disallow assembler to change the order of instructions in the block that follows. As the implemented AsmParser requires .set directive to have the following syntax:
2015 Jul 30
0
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
Thanks. This is making a lot more sense now and it's looking like this issue isn't Mips specific. Here's the IR dump before simple register coalescing (note: I've patched the IR printer to print the contents of the regmask): 4480B %vreg260<def> = LDC1 %vreg253, <cp#3>[TF=6]; mem:LD8[ConstantPool] AFGR64:%vreg260 GPR32:%vreg253 4496B %vreg261<def> = FMUL_D32
2017 Jul 11
4
[LLD] Linker Relaxation
By the way, since this is an optional code relaxation, we can think about it later. The first thing I would do is to add RISC-V support to lld without code shrinking relaxations, which I believe is doable by at most a few hundreds lines of code. On Wed, Jul 12, 2017 at 3:21 AM, Rui Ueyama <ruiu at google.com> wrote: > On Tue, Jul 11, 2017 at 9:14 PM, Bruce Hoult via llvm-dev < >
2017 Jul 11
8
[LLD] Linker Relaxation
Here's an example using the gcc toolchain for embedded 32 bit RISC-V (my HiFive1 board): #include <stdio.h> int foo(int i){ if (i < 100){ printf("%d\n", i); } return i; } int main(){ foo(10); return 0; } After compiling to a .o with -O2 -march=RV32IC we get (just looking at foo) 00000000 <foo>: 0: 1141 addi sp,sp,-16
2019 Mar 13
2
Need help implementing relocations
Tim, Thanks for the explanation. "it tells the linker to insert the address of date when converting this .o file into a final executable." Which utility do you use to convert .o to .elf and insert the address of 'date'? llvm-objcopy? ________________________________ From: Tim Northover <t.p.northover at gmail.com> Sent: Wednesday, March 13, 2019 3:20 AM To: Josh Sharp Cc:
2007 Jul 12
1
[LLVMdev] backend problem with LiveInterval::removeRange
Hi all, When compiling some programs using the Mips backend i'm getting this assert message on lib/CodeGen/LiveInterval.cpp:227: "Range is not entirely in interval!" I don't know yet if it's something that is missing on the backend code or why the range to be removed it outside the interval, does anyone have any clue? A more detailed output is attached. The program i tried
2019 Mar 13
2
Need help implementing relocations
Hi all, I have reached the relocation phase of my backend implementation and I'm having some trouble. The LLVM code I'm trying to compile is this: %struct.Date = type { i32, i32, i32 } @date = global %struct.Date { i32 2012, i32 10, i32 120000 }, align 4 ; Function Attrs: nounwind define i32 @foo() #0 { %1 = load i32, i32* getelementptr inbounds (%struct.Date, %struct.Date* @date, i32
2010 Jan 28
1
[LLVMdev] question when -march=mips
Hi everyone The c code is like below extern int function_0(int, int); int main(){ return function_0(8, 9); } I compile it as below llvm-gcc main.c -emit-llvm -c -O3 -o main.bc llc main.bc -relocation-model=static -march=mips -O0 -o main.s It seems no argument is provided to function_0 ... addiu $sp, $sp, -8 sw $ra, 0($sp) jal function_0
2012 Nov 16
1
[LLVMdev] Handling segmented instruction space in backend for custom target
Hi all, I'm building a backend for a custom target, and I'm trying to figure out how to handle global and external target address with my architecture's call instructions. This arch. has 16-bit addresses into a segmented address space, and to do a direct call I need to set both an instruction counter (IC, 10 bits wide) and an instruction segment register (ISR, 6 bits wide). My CALL
2019 Jan 18
0
[klibc:master] mips64: compile with -mno-abicalls
Commit-ID: 0a14ced5d7d0c23ece5d2828cbdff6cb1c589b8d Gitweb: http://git.kernel.org/?p=libs/klibc/klibc.git;a=commit;h=0a14ced5d7d0c23ece5d2828cbdff6cb1c589b8d Author: James Cowgill <james.cowgill at mips.com> AuthorDate: Fri, 2 Mar 2018 14:48:21 +0000 Committer: Ben Hutchings <ben at decadent.org.uk> CommitDate: Wed, 2 Jan 2019 03:08:04 +0000 [klibc] mips64: compile with
2005 Jul 27
0
Help! Problem with NT PDC on 3.0.14a
Hello, We are trying to add a 2nd samba server to our domain. We are using an NT 4.0 PDC and connecting to the PDC using winbind. Our network is relatively small - 25 computers. We have no Active Directory servers, no WINS servers, and the existing samba server running 3.0.11 has been running for 18 months with no issues. We are completely stuck trying to add a second server. We've
2012 Nov 11
2
[LLVMdev] Tracing nodes in selectionDAG to final code...
Hello everyone. I use this command clang -emit-llvm hello.c -c -o hello.bc llc hello.bc -march=mipsel -relocation-model=static -o hello.s to produce this MIPS code: .section .mdebug.abi32 .previous .file "hello.bc" .text .globl main .align 2 .type main, at function .set nomips16 # @main .ent main main: .cfi_startproc .frame $sp,32,$ra .mask 0x80000000,-4 .fmask
2013 Apr 25
1
[LLVMdev] issues with InlineAsm class and #APP/#NOAPP
I'm happy to send you my patch as it stands today. It's not cleaned up yet all or tested thoroughtly but you can look at what I'm doing and maybe suggest some alternate paths and if it's not a matter of redoing everything, I would consider making some changes. Here is a sample stub: Consider this line of code: extern float fpff(float); We have no idea if this is a mips16 or
2012 Dec 28
1
[LLVMdev] [PATCH] LLVM build failure on OpenBSD/mips64
I'm just passing this patch on to the list as I know Brian is busy and I had proded him to file the bug report. http://llvm.org/bugs/show_bug.cgi?id=14721 "binutils on OpenBSD is quite old, which causes the build on mips64el to fail on MipsJITInfo.cpp - it complains of illegal operands. The attachment patches it so that it will build. All the patch does is replace the register aliases