Andrei Safronov via llvm-dev
2019-Mar-06 11:29 UTC
[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend
Hello, I'm from Espressif Systems company, software department. Our company develops processors based on Xtensa architecture like ESP32 and ESP8266. We propose the integration of a backend targeting Xtensa architecture. We started to develop LLVM Xtensa backend almost a year ago. The reason was that we saw a demand from our large developers community. Currently only GNU compiler supports Xtensa architecture. The company has approved me to develop and maintain Xtensa backend. We already have the initial version of the Xtensa backend, based on LLVM Compiler Infrastructure, release 6.0.0. It was successfully tested using GCC torture testsuite and multiple applications. These are the links to LLVM and Clang repositories. https://github.com/espressif/llvm-xtensa https://github.com/espressif/clang-xtensa Current version can generate Xtensa assembly code as output, not object files yet, and has to be used together with GNU Binutils and GCC-built libraries to create object and binary files. Xtensa backend features implemented: - Xtensa target description(Xtnesa.td, XtensaTargetMachine.cpp, XtensaSubTarget.cpp) - ISA desciption (XtensaInstrInfo.td, XtensaInstrFormats.td, XtensaREgisterInfo.td) - Xtensa Call ABI (XtensaCallingConv.td, XtensaFrameLowering.cpp) - ASM printer/parser(XtesaAsmPrinter.cpp, XtensaInstrPrinter.cpp, XtensaAsmParser.cpp) Xtensa architecture features implemented in compiler: - Xtensa Core Architecture instructions - Code Density option - Windowed Register option - Floating-Point Coprocessor option - Boolean option (only a subset of instructions) - Thread Pointer option - atomic operations Current Xtensa target list: - support Xtensa LX6 target (ESP32) by default Compiler optimization levels include O0/O1/O2/O3/Os options. With LLVM community approval, my next plans will be - rebasing on the upstream version of LLVM. - object code generation (XtensaMC package) - implement test cases - support for LX106 target (ESP8266) - improvements of generated code performance - support for zero-overhead loop option - MAC16 option There were some discussions about implementation of the Xtensa backend and attempt to implement it: http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html Also there were attempts to implement a LLVM Xtensa backend, but recently I found only one actual link: https://github.com/jdiez17/llvm-xtensa All comments and suggesions are welcome! Andrei Safronov -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190306/276b2b85/attachment.html>
Dan Kortschak via llvm-dev
2019-Mar-06 21:42 UTC
[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend
This is welcome news to me. We use ESP8266 (yes, not ESP32, but your future plans include the older MCU) for an IOT system in conjunction with RPi machines. The language that we target in preference is Go, but obviously currently use C++ for the ESPs. We'd like to use Go for the ESPs via the tinygo.org project, but this depends on clang/llvm support of the MCU target. thanks Dan Kortschak I recently asked here about the prior work https://lists.llvm.org/piper mail/llvm-dev/2019-February/130169.html. On Wed, 2019-03-06 at 14:29 +0300, Andrei Safronov via llvm-dev wrote:> Hello, > > I'm from Espressif Systems company, software department. Our company > develops processors based on Xtensa architecture like ESP32 and > ESP8266. > We propose the integration of a backend targeting Xtensa > architecture. > > We started to develop LLVM Xtensa backend almost a year ago. The > reason > was that we saw a demand from our large developers community. > Currently > only GNU compiler supports Xtensa architecture. The company has > approved > me to develop and maintain Xtensa backend. > > We already have the initial version of the Xtensa backend, based on > LLVM > Compiler Infrastructure, release 6.0.0. It was successfully tested > using > GCC torture testsuite and multiple applications. > > These are the links to LLVM and Clang repositories. > > https://github.com/espressif/llvm-xtensa > https://github.com/espressif/clang-xtensa > > Current version can generate Xtensa assembly code as output, not > object > files yet, and has to be used together with GNU Binutils and GCC- > built > libraries to create object and binary files. > > Xtensa backend features implemented: > > - Xtensa target description(Xtnesa.td, XtensaTargetMachine.cpp, > XtensaSubTarget.cpp) > - ISA desciption (XtensaInstrInfo.td, XtensaInstrFormats.td, > XtensaREgisterInfo.td) > - Xtensa Call ABI (XtensaCallingConv.td, XtensaFrameLowering.cpp) > - ASM printer/parser(XtesaAsmPrinter.cpp, XtensaInstrPrinter.cpp, > XtensaAsmParser.cpp) > > Xtensa architecture features implemented in compiler: > > - Xtensa Core Architecture instructions > - Code Density option > - Windowed Register option > - Floating-Point Coprocessor option > - Boolean option (only a subset of instructions) > - Thread Pointer option > - atomic operations > > Current Xtensa target list: > > - support Xtensa LX6 target (ESP32) by default > > Compiler optimization levels include O0/O1/O2/O3/Os options. > > With LLVM community approval, my next plans will be > > - rebasing on the upstream version of LLVM. > - object code generation (XtensaMC package) > - implement test cases > - support for LX106 target (ESP8266) > - improvements of generated code performance > - support for zero-overhead loop option > - MAC16 option > > There were some discussions about implementation of the Xtensa > backend > and attempt to implement it: > http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html > http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html > > Also there were attempts to implement a LLVM Xtensa backend, but > recently I found only one actual link: > https://github.com/jdiez17/llvm-xtensa > > All comments and suggesions are welcome! > > Andrei Safronov > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
James Y Knight via llvm-dev
2019-Mar-06 22:31 UTC
[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend
Sounds like a good idea to me! It seems there's plenty of interest in this architecture.>From a quick glance at your existing code, it looks like you haven't addedany llvm tests -- that'll certainly be a requirement. But barring some particular reason why it's not feasible, I think that having object-file generation working is basically considered a requirement for new architectures. (It's also not clear to me why you cannot with your current code, it looks like instruction definitions already have their encodings specified and such). If you haven't yet, you ought to check out at the great patch series that Alex Bradbury created to demonstrate the addition of RISCV support to LLVM, as a guide to what order it probably makes sense to make the changes, and how to split the changes into reviewable pieces for upstreaming: https://github.com/lowRISC/riscv-llvm I'd suggest as your first step, you should work on getting just the Asm/MC layer rebased onto trunk and working for the core ISA for your target -- able to parse and print assembly, both textual and object files -- with a full suite of test-cases at each step. Just like the first ~10 patches in the above patchset. On Wed, Mar 6, 2019 at 6:29 AM Andrei Safronov via llvm-dev < llvm-dev at lists.llvm.org> wrote:> Hello, > > I'm from Espressif Systems company, software department. Our company > develops processors based on Xtensa architecture like ESP32 and ESP8266. We > propose the integration of a backend targeting Xtensa architecture. > > We started to develop LLVM Xtensa backend almost a year ago. The reason > was that we saw a demand from our large developers community. Currently > only GNU compiler supports Xtensa architecture. The company has approved me > to develop and maintain Xtensa backend. > > We already have the initial version of the Xtensa backend, based on LLVM > Compiler Infrastructure, release 6.0.0. It was successfully tested using > GCC torture testsuite and multiple applications. > > These are the links to LLVM and Clang repositories. > > https://github.com/espressif/llvm-xtensa > https://github.com/espressif/clang-xtensa > > Current version can generate Xtensa assembly code as output, not object > files yet, and has to be used together with GNU Binutils and GCC-built > libraries to create object and binary files. > > Xtensa backend features implemented: > > - Xtensa target description(Xtnesa.td, XtensaTargetMachine.cpp, > XtensaSubTarget.cpp) > - ISA desciption (XtensaInstrInfo.td, XtensaInstrFormats.td, > XtensaREgisterInfo.td) > - Xtensa Call ABI (XtensaCallingConv.td, XtensaFrameLowering.cpp) > - ASM printer/parser(XtesaAsmPrinter.cpp, XtensaInstrPrinter.cpp, > XtensaAsmParser.cpp) > > Xtensa architecture features implemented in compiler: > > - Xtensa Core Architecture instructions > - Code Density option > - Windowed Register option > - Floating-Point Coprocessor option > - Boolean option (only a subset of instructions) > - Thread Pointer option > - atomic operations > > Current Xtensa target list: > > - support Xtensa LX6 target (ESP32) by default > > Compiler optimization levels include O0/O1/O2/O3/Os options. > > With LLVM community approval, my next plans will be > > - rebasing on the upstream version of LLVM. > - object code generation (XtensaMC package) > - implement test cases > - support for LX106 target (ESP8266) > - improvements of generated code performance > - support for zero-overhead loop option > - MAC16 option > > There were some discussions about implementation of the Xtensa backend and > attempt to implement it: > http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html > http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html > > Also there were attempts to implement a LLVM Xtensa backend, but recently > I found only one actual link: > https://github.com/jdiez17/llvm-xtensa > > All comments and suggesions are welcome! > > Andrei Safronov > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190306/55909bf5/attachment.html>
Andrei Safronov via llvm-dev
2019-Mar-07 13:12 UTC
[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend
Hello, Thank you for your interest. We are planning to add support for ESP8266 in the near future. Best regards, Andrey Safronov 07.03.2019 0:42, Dan Kortschak пишет:> This is welcome news to me. > > We use ESP8266 (yes, not ESP32, but your future plans include the older > MCU) for an IOT system in conjunction with RPi machines. The language > that we target in preference is Go, but obviously currently use C++ for > the ESPs. We'd like to use Go for the ESPs via the tinygo.org project, > but this depends on clang/llvm support of the MCU target. > > thanks > Dan Kortschak > > I recently asked here about the prior work https://lists.llvm.org/piper > mail/llvm-dev/2019-February/130169.html. > > On Wed, 2019-03-06 at 14:29 +0300, Andrei Safronov via llvm-dev wrote: >> Hello, >> >> I'm from Espressif Systems company, software department. Our company >> develops processors based on Xtensa architecture like ESP32 and >> ESP8266. >> We propose the integration of a backend targeting Xtensa >> architecture. >> >> We started to develop LLVM Xtensa backend almost a year ago. The >> reason >> was that we saw a demand from our large developers community. >> Currently >> only GNU compiler supports Xtensa architecture. The company has >> approved >> me to develop and maintain Xtensa backend. >> >> We already have the initial version of the Xtensa backend, based on >> LLVM >> Compiler Infrastructure, release 6.0.0. It was successfully tested >> using >> GCC torture testsuite and multiple applications. >> >> These are the links to LLVM and Clang repositories. >> >> https://github.com/espressif/llvm-xtensa >> https://github.com/espressif/clang-xtensa >> >> Current version can generate Xtensa assembly code as output, not >> object >> files yet, and has to be used together with GNU Binutils and GCC- >> built >> libraries to create object and binary files. >> >> Xtensa backend features implemented: >> >> - Xtensa target description(Xtnesa.td, XtensaTargetMachine.cpp, >> XtensaSubTarget.cpp) >> - ISA desciption (XtensaInstrInfo.td, XtensaInstrFormats.td, >> XtensaREgisterInfo.td) >> - Xtensa Call ABI (XtensaCallingConv.td, XtensaFrameLowering.cpp) >> - ASM printer/parser(XtesaAsmPrinter.cpp, XtensaInstrPrinter.cpp, >> XtensaAsmParser.cpp) >> >> Xtensa architecture features implemented in compiler: >> >> - Xtensa Core Architecture instructions >> - Code Density option >> - Windowed Register option >> - Floating-Point Coprocessor option >> - Boolean option (only a subset of instructions) >> - Thread Pointer option >> - atomic operations >> >> Current Xtensa target list: >> >> - support Xtensa LX6 target (ESP32) by default >> >> Compiler optimization levels include O0/O1/O2/O3/Os options. >> >> With LLVM community approval, my next plans will be >> >> - rebasing on the upstream version of LLVM. >> - object code generation (XtensaMC package) >> - implement test cases >> - support for LX106 target (ESP8266) >> - improvements of generated code performance >> - support for zero-overhead loop option >> - MAC16 option >> >> There were some discussions about implementation of the Xtensa >> backend >> and attempt to implement it: >> http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html >> http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html >> >> Also there were attempts to implement a LLVM Xtensa backend, but >> recently I found only one actual link: >> https://github.com/jdiez17/llvm-xtensa >> >> All comments and suggesions are welcome! >> >> Andrei Safronov >> >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org >> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
Andrei Safronov via llvm-dev
2019-Mar-07 17:47 UTC
[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend
Hello, James, Thank you very much for your advices! The next step in compiler development on Espressif is object file generation. There are no essential problems with this step, it will be implemented in nearest future. Currently Xtensa backend is able to print and parse assembly, I used about 1300 tests from gcc torture testsuite and GNU binutils to debug assembly output and now all tests could be compiled and executed successfully. So, with object file generation Xtensa backend will be significally closer to be used in real projects, but I'm agree that it is not ready yet for upstreaming. There is no llvm tests and also it is hard to review such big amount of code. So I need to do something with these issues. I reviewed integration process of the RISC-V backend, which you mentioned. Did I understand correctly that you suggest to split the proposed Xtensa backend into ordered patches, each of which defines some backend functionality (starting from Asm/MC layer)that is easy to review? And also include in each patch some set of tests to verify such functionality? Best regards, Andrei Safronov 07.03.2019 1:31, James Y Knight пишет:> Sounds like a good idea to me! It seems there's plenty of interest in > this architecture. > > From a quick glance at your existing code, it looks like you haven't > added any llvm tests -- that'll certainly be a requirement. But > barring some particular reason why it's not feasible, I think that > having object-file generation working is basically considered a > requirement for new architectures. (It's also not clear to me why you > cannot with your current code, it looks like instruction definitions > already have their encodings specified and such). > > If you haven't yet, you ought to check out at the great patch series > that Alex Bradbury created to demonstrate the addition of RISCV > support to LLVM, as a guide to what order it probably makes sense to > make the changes, and how to split the changes into reviewable pieces > for upstreaming: https://github.com/lowRISC/riscv-llvm > > I'd suggest as your first step, you should work on getting just the > Asm/MC layer rebased onto trunk and working for the core ISA for your > target -- able to parse and print assembly, both textual and object > files -- with a full suite of test-cases at each step. Just like the > first ~10 patches in the above patchset. > > > > On Wed, Mar 6, 2019 at 6:29 AM Andrei Safronov via llvm-dev > <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > Hello, > > I'm from Espressif Systems company, software department. Our > company develops processors based on Xtensa architecture like > ESP32 and ESP8266. We propose the integration of a backend > targeting Xtensa architecture. > > We started to develop LLVM Xtensa backend almost a year ago. The > reason was that we saw a demand from our large developers > community. Currently only GNU compiler supports Xtensa > architecture. The company has approved me to develop and maintain > Xtensa backend. > > We already have the initial version of the Xtensa backend, based > on LLVM Compiler Infrastructure, release 6.0.0. It was > successfully tested using GCC torture testsuite and multiple > applications. > > These are the links to LLVM and Clang repositories. > > https://github.com/espressif/llvm-xtensa > https://github.com/espressif/clang-xtensa > > Current version can generate Xtensa assembly code as output, not > object files yet, and has to be used together with GNU Binutils > and GCC-built libraries to create object and binary files. > > Xtensa backend features implemented: > > - Xtensa target description(Xtnesa.td, XtensaTargetMachine.cpp, > XtensaSubTarget.cpp) > - ISA desciption (XtensaInstrInfo.td, XtensaInstrFormats.td, > XtensaREgisterInfo.td) > - Xtensa Call ABI (XtensaCallingConv.td, XtensaFrameLowering.cpp) > - ASM printer/parser(XtesaAsmPrinter.cpp, XtensaInstrPrinter.cpp, > XtensaAsmParser.cpp) > > Xtensa architecture features implemented in compiler: > > - Xtensa Core Architecture instructions > - Code Density option > - Windowed Register option > - Floating-Point Coprocessor option > - Boolean option (only a subset of instructions) > - Thread Pointer option > - atomic operations > > Current Xtensa target list: > > - support Xtensa LX6 target (ESP32) by default > > Compiler optimization levels include O0/O1/O2/O3/Os options. > > With LLVM community approval, my next plans will be > > - rebasing on the upstream version of LLVM. > - object code generation (XtensaMC package) > - implement test cases > - support for LX106 target (ESP8266) > - improvements of generated code performance > - support for zero-overhead loop option > - MAC16 option > > There were some discussions about implementation of the Xtensa > backend and attempt to implement it: > http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html > http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html > > Also there were attempts to implement a LLVM Xtensa backend, but > recently I found only one actual link: > https://github.com/jdiez17/llvm-xtensa > > All comments and suggesions are welcome! > > Andrei Safronov > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190307/9c4435c2/attachment.html>
Anmol Paralkar (anmparal) via llvm-dev
2019-Mar-08 22:44 UTC
[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend
Hello Andrei, Thank you for the LLVM Xtensa work and the post. Cisco Systems would be glad to support any upstreaming effort for this work in terms of reviews, tests, object file generation, further development, etc. Best Regards, Anmol P. Paralkar From: llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of Andrei Safronov via llvm-dev <llvm-dev at lists.llvm.org> Reply-To: Andrei Safronov <safronov at espressif.com> Date: Wednesday, March 6, 2019 at 5:30 AM To: "llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org> Subject: [llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend Hello, I'm from Espressif Systems company, software department. Our company develops processors based on Xtensa architecture like ESP32 and ESP8266. We propose the integration of a backend targeting Xtensa architecture. We started to develop LLVM Xtensa backend almost a year ago. The reason was that we saw a demand from our large developers community. Currently only GNU compiler supports Xtensa architecture. The company has approved me to develop and maintain Xtensa backend. We already have the initial version of the Xtensa backend, based on LLVM Compiler Infrastructure, release 6.0.0. It was successfully tested using GCC torture testsuite and multiple applications. These are the links to LLVM and Clang repositories. https://github.com/espressif/llvm-xtensa https://github.com/espressif/clang-xtensa Current version can generate Xtensa assembly code as output, not object files yet, and has to be used together with GNU Binutils and GCC-built libraries to create object and binary files. Xtensa backend features implemented: - Xtensa target description(Xtnesa.td, XtensaTargetMachine.cpp, XtensaSubTarget.cpp) - ISA desciption (XtensaInstrInfo.td, XtensaInstrFormats.td, XtensaREgisterInfo.td) - Xtensa Call ABI (XtensaCallingConv.td, XtensaFrameLowering.cpp) - ASM printer/parser(XtesaAsmPrinter.cpp, XtensaInstrPrinter.cpp, XtensaAsmParser.cpp) Xtensa architecture features implemented in compiler: - Xtensa Core Architecture instructions - Code Density option - Windowed Register option - Floating-Point Coprocessor option - Boolean option (only a subset of instructions) - Thread Pointer option - atomic operations Current Xtensa target list: - support Xtensa LX6 target (ESP32) by default Compiler optimization levels include O0/O1/O2/O3/Os options. With LLVM community approval, my next plans will be - rebasing on the upstream version of LLVM. - object code generation (XtensaMC package) - implement test cases - support for LX106 target (ESP8266) - improvements of generated code performance - support for zero-overhead loop option - MAC16 option There were some discussions about implementation of the Xtensa backend and attempt to implement it: http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html Also there were attempts to implement a LLVM Xtensa backend, but recently I found only one actual link: https://github.com/jdiez17/llvm-xtensa All comments and suggesions are welcome! Andrei Safronov -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190308/f177e0f1/attachment.html>
Andrei Safronov via llvm-dev
2019-Mar-11 00:20 UTC
[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend
Hello Anmol, Thank you for your support. I think that community help could accelerate integration of backend, so I will keep in mind your suggestions. By the way it will useful to know what kind of task do you solve with Xtensa processors and also which Xtensa configuration do you use(of cause if it is not confidential information). Such information could help to tune some aspects of the Xtensa backend. Best regards, Andrei Safronov 09.03.2019 1:44, Anmol Paralkar (anmparal) пишет:> > Hello Andrei, > > Thank you for the LLVM Xtensa work and the post. Cisco Systems would > be glad to support any upstreaming effort for this work in terms of > reviews, tests, object file generation, further development, etc. > > Best Regards, > > Anmol P. Paralkar > > *From: *llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of Andrei > Safronov via llvm-dev <llvm-dev at lists.llvm.org> > *Reply-To: *Andrei Safronov <safronov at espressif.com> > *Date: *Wednesday, March 6, 2019 at 5:30 AM > *To: *"llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org> > *Subject: *[llvm-dev] [RFC] Tensilica Xtensa (ESP32) backend > > Hello, > > I'm from Espressif Systems company, software department. Our company > develops processors based on Xtensa architecture like ESP32 and > ESP8266. We propose the integration of a backend targeting Xtensa > architecture. > > We started to develop LLVM Xtensa backend almost a year ago. The > reason was that we saw a demand from our large developers community. > Currently only GNU compiler supports Xtensa architecture. The company > has approved me to develop and maintain Xtensa backend. > > We already have the initial version of the Xtensa backend, based on > LLVM Compiler Infrastructure, release 6.0.0. It was successfully > tested using GCC torture testsuite and multiple applications. > > These are the links to LLVM and Clang repositories. > > https://github.com/espressif/llvm-xtensa > https://github.com/espressif/clang-xtensa > > Current version can generate Xtensa assembly code as output, not > object files yet, and has to be used together with GNU Binutils and > GCC-built libraries to create object and binary files. > > Xtensa backend features implemented: > > - Xtensa target description(Xtnesa.td, XtensaTargetMachine.cpp, > XtensaSubTarget.cpp) > - ISA desciption (XtensaInstrInfo.td, XtensaInstrFormats.td, > XtensaREgisterInfo.td) > - Xtensa Call ABI (XtensaCallingConv.td, XtensaFrameLowering.cpp) > - ASM printer/parser(XtesaAsmPrinter.cpp, XtensaInstrPrinter.cpp, > XtensaAsmParser.cpp) > > Xtensa architecture features implemented in compiler: > > - Xtensa Core Architecture instructions > - Code Density option > - Windowed Register option > - Floating-Point Coprocessor option > - Boolean option (only a subset of instructions) > - Thread Pointer option > - atomic operations > > Current Xtensa target list: > > - support Xtensa LX6 target (ESP32) by default > > Compiler optimization levels include O0/O1/O2/O3/Os options. > > With LLVM community approval, my next plans will be > > - rebasing on the upstream version of LLVM. > - object code generation (XtensaMC package) > - implement test cases > - support for LX106 target (ESP8266) > - improvements of generated code performance > - support for zero-overhead loop option > - MAC16 option > > There were some discussions about implementation of the Xtensa backend > and attempt to implement it: > http://lists.llvm.org/pipermail/llvm-dev/2018-July/124789.html > http://lists.llvm.org/pipermail/llvm-dev/2018-April/122676.html > > Also there were attempts to implement a LLVM Xtensa backend, but > recently I found only one actual link: > https://github.com/jdiez17/llvm-xtensa > > All comments and suggesions are welcome! > > Andrei Safronov >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190311/bd7d4a2b/attachment.html>