search for: xtensa

Hello, I'm from Espressif Systems company, software department. Our company develops processors based on Xtensa architecture like ESP32 and ESP8266. We propose the integration of a backend targeting Xtensa architecture. We started to develop LLVM Xtensa backend almost a year ago. The reason was that we saw a demand from our large developers community. Currently only GNU compiler supports Xtensa architect...

Hello, James, Thank you very much for your advices! The next step in compiler development on Espressif is object file generation. There are no essential problems with this step, it will be implemented in nearest future. Currently Xtensa backend is able to print and parse assembly, I used about 1300 tests from gcc torture testsuite and GNU binutils to debug assembly output and now all tests could be compiled and executed successfully. So, with object file generation Xtensa backend will be significally closer to be used in real...

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to do the rest of the work. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- v1 -> v2: - factored out similar logic between vp and bsp...

These chipsets include the VP2 engine which is composed of a bitstream processor (BSP) that decodes H.264 and a video processor (VP) which can do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are driven by separate xtensa chips embedded in the hardware. This patch provides the mechanism to load the kernel for the xtensa chips and provide the necessary interactions to do the rest of the work. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- This patch applies on top of nouveau/master (16a41bcc8). Thi...

Can you give me some insights to implement the windowed calling convention in this xtensa backend : https://github.com/afonso360/llvm-xtensa/tree/xtensa/lib/Target/Xtensa ? For now, only the simpler CALL0 calling convention is implemented. In order to implement the windowed calling convention, every routines must start with the ENTRY instruction which increments the register window po...

...0x100) (since we send the size >> 8) and also ALIGN(fw->size, 0x1000) (page size, who knows), with no effect. Might as well just leave it hard-coded at 0x40000. Please make sure that this hits 3.11, otherwise it will not be useable for video decoding. drivers/gpu/drm/nouveau/core/engine/xtensa.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/core/engine/xtensa.c b/drivers/gpu/drm/nouveau/core/engine/xtensa.c index 0639bc5..5f6ede7 100644 --- a/drivers/gpu/drm/nouveau/core/engine/xtensa.c +++ b/drivers/gpu/drm/nouveau/core/engine/xtensa....

This patchset centralizes the firmware-loading procedure to one set of functions instead of having each engine load its firmware as it pleases. This helps ensure that all firmware comes from the same place, namely nvidia/<chip>/. This changes where the firmware is fetched from for falcon/xtensa/bios, but these locations never seemed to have been official anyway. Also for most (all?) chips supported by Nouveau there is corresponding internal firmware, so disruption should be minimal/non-existent. If this assumption is wrong, feel free to drop patches 3-5. At the very least, firmware offici...

...mirkin at alum.mit.edu> wrote: >> These chipsets include the VP2 engine which is composed of a bitstream >> processor (BSP) that decodes H.264 and a video processor (VP) which can >> do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are >> driven by separate xtensa chips embedded in the hardware. This patch >> provides the mechanism to load the kernel for the xtensa chips and >> provide the necessary interactions to do the rest of the work. >> >> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> >> --- >> >>...

Hi, I am trying to build asterisk with xtensa compiler on embedded platform. I am trying to integrate my driver code to asterisk. For this tying to call driver code IOCTLs from chan_dahdi instead of dahdi IOCTLs. While compiling asterisk with xtensa, Observed chan_dahdi is not compiling [chan_dahdi.so is not creating].But with default sett...

...it.edu> wrote: >>> These chipsets include the VP2 engine which is composed of a bitstream >>> processor (BSP) that decodes H.264 and a video processor (VP) which can >>> do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are >>> driven by separate xtensa chips embedded in the hardware. This patch >>> provides the mechanism to load the kernel for the xtensa chips and >>> provide the necessary interactions to do the rest of the work. >>> >>> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> >>> --...

...entralizes the firmware-loading procedure to one set of functions > instead of having each engine load its firmware as it pleases. This helps ensure > that all firmware comes from the same place, namely nvidia/<chip>/. > > This changes where the firmware is fetched from for falcon/xtensa/bios, but > these locations never seemed to have been official anyway. Also for most (all?) > chips supported by Nouveau there is corresponding internal firmware, so > disruption should be minimal/non-existent. If this assumption is wrong, feel > free to drop patches 3-5. At the very le...

...rk.kernel.org/patch/10450037/ > > v8->v9: * Restoring the '-pipe' parameter (Rasmus) > * Adding Kees's tested-by tag (Kees) > > v7->v8: * Add acks (Masahiro, Max) > * Rebase on 4.19 (Ingo) > > v6->v7: * Fix context switch tracking (Ingo) > * Fix xtensa build error (Ingo) > * Rebase on 4.18-rc8 > > v5->v6: * Removing more code from jump-labels (PeterZ) > * Fix build issue on i386 (0-day, PeterZ) > > v4->v5: * Makefile fixes (Masahiro, Sam) > > v3->v4: * Changed naming of macros in 2 patches (PeterZ) > * Mi...

From: Thierry Reding <treding at nvidia.com> The semantics of do_div() are (see include/asm-generic/div64.h): uint32_t do_div(uint64_t *n, uint32_t base) Using a different type will therefore cause the following warning (as seen on xtensa/allmodconfig): CC [M] drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.o In file included from arch/xtensa/include/generated/asm/div64.h:1:0, from include/linux/kernel.h:124, from include/linux/list.h:8, from include/linux/preempt.h:10,...

...lia Mirkin <imirkin at alum.mit.edu> wrote: > These chipsets include the VP2 engine which is composed of a bitstream > processor (BSP) that decodes H.264 and a video processor (VP) which can > do iDCT/mo-comp/etc for MPEG1/2, H.264, and VC-1. Both of these are > driven by separate xtensa chips embedded in the hardware. This patch > provides the mechanism to load the kernel for the xtensa chips and > provide the necessary interactions to do the rest of the work. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > > This patch applies on top of...

Use the newly added u64_to_user_pointer a bit more frequently. Signed-off-by: Joe Perches <joe at perches.com> --- drivers/gpu/drm/armada/armada_gem.c | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 7 ++++--- drivers/gpu/drm/tegra/drm.c | 15 ++++++++------- drivers/gpu/drm/vc4/vc4_bo.c | 4 ++-- drivers/gpu/drm/vc4/vc4_gem.c | 10 +++++-----

Use the newly added u64_to_user_pointer a bit more frequently. Signed-off-by: Joe Perches <joe at perches.com> --- drivers/gpu/drm/armada/armada_gem.c | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 7 ++++--- drivers/gpu/drm/tegra/drm.c | 15 ++++++++------- drivers/gpu/drm/vc4/vc4_bo.c | 4 ++-- drivers/gpu/drm/vc4/vc4_gem.c | 10 +++++-----

...| 1 - arch/sparc/include/asm/processor_32.h | 1 - arch/sparc/include/asm/processor_64.h | 1 - arch/tile/include/asm/processor.h | 2 -- arch/unicore32/include/asm/processor.h | 1 - arch/x86/include/asm/processor.h | 2 -- arch/x86/um/asm/processor.h | 1 - arch/xtensa/include/asm/processor.h | 1 - include/linux/sched.h | 4 ++++ 33 files changed, 5 insertions(+), 38 deletions(-) diff --git a/arch/alpha/include/asm/processor.h b/arch/alpha/include/asm/processor.h index 31e8dbe..2fec2de 100644 --- a/arch/alpha/include/asm/processor.h +++ b/...

...| 1 - arch/sparc/include/asm/processor_32.h | 1 - arch/sparc/include/asm/processor_64.h | 1 - arch/tile/include/asm/processor.h | 2 -- arch/unicore32/include/asm/processor.h | 1 - arch/x86/include/asm/processor.h | 2 -- arch/x86/um/asm/processor.h | 1 - arch/xtensa/include/asm/processor.h | 1 - include/linux/sched.h | 4 ++++ 33 files changed, 5 insertions(+), 38 deletions(-) diff --git a/arch/alpha/include/asm/processor.h b/arch/alpha/include/asm/processor.h index 31e8dbe..2fec2de 100644 --- a/arch/alpha/include/asm/processor.h +++ b/...

...xx arm: define __smp_xxx blackfin: define __smp_xxx ia64: define __smp_xxx metag: define __smp_xxx mips: define __smp_xxx s390: define __smp_xxx sh: define __smp_xxx, fix smp_store_mb for !SMP sparc: define __smp_xxx tile: define __smp_xxx xtensa: define __smp_xxx x86: define __smp_xxx asm-generic: implement virt_xxx memory barriers Revert "virtio_ring: Update weak barriers to use dma_wmb/rmb" virtio_ring: update weak barriers to use virt_xxx sh: support 1 and 2 byte xchg sh: move xchg_cmpxchg t...

...xx arm: define __smp_xxx blackfin: define __smp_xxx ia64: define __smp_xxx metag: define __smp_xxx mips: define __smp_xxx s390: define __smp_xxx sh: define __smp_xxx, fix smp_store_mb for !SMP sparc: define __smp_xxx tile: define __smp_xxx xtensa: define __smp_xxx x86: define __smp_xxx asm-generic: implement virt_xxx memory barriers Revert "virtio_ring: Update weak barriers to use dma_wmb/rmb" virtio_ring: update weak barriers to use virt_xxx sh: support 1 and 2 byte xchg sh: move xchg_cmpxchg t...