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Martin J. O'Riordan via llvm-dev

2016-Jul-08 11:58 UTC

[llvm-dev] Dynamic selection of assembly mnemonic strings

Thanks for the quick answer Bruce.

 

So far as I can tell (from a quick read), this is really for integrated
assemblers/disassemblers - but we use an external assembler.  When invoking
clang we would provide ‘-mcpu=chip_v1’ or ‘-mcpu=chip_v2’, and the mnemonic
‘LD32’ is only valid when compiling for ‘chip_v1’, while ‘LD.32’ is only valid
when compiling for ‘chip_v2’.  But I will study the mnemonic aliasing carefully
to see if it does provide what I need.

 

All the best,

 

            MartinO

 

From: bruce.hoult at gmail.com [mailto:bruce.hoult at gmail.com] On Behalf Of
Bruce Hoult
Sent: 08 July 2016 12:32
To: Martin J. O'Riordan <Martin.ORiordan at movidius.com>
Cc: LLVM Developers <llvm-dev at lists.llvm.org>
Subject: Re: [llvm-dev] Dynamic selection of assembly mnemonic strings

 

Do instruction aliases do the job?

 

http://llvm.org/docs/CodeGenerator.html#instruction-alias-processing

 

Is it ok to have the same source file use LD32 in one instruction but LD.32 in
the next one, or do you want different modes?

 

 

On Fri, Jul 8, 2016 at 2:24 PM, Martin J. O'Riordan via llvm-dev
<llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> >
wrote:

Hi LLVM Dev,

 

I have an old problem that I’ve wanted to clean-up for some time.  Our chip has
gone through a number of iterations in the past few years, but with each
revision there have been changes to some of the mnemonics for instructions. 
These are mostly very simple, for example we had a 32-bit load from memory
instruction named ‘LD32’ in one version of the chip, but for a later version
this was changed to ‘LD.32’.

 

The semantics and schedule remained the same, but in the TD file I had to
introduce two ‘def’s for this (actually, I abstract a bit more and use a
‘defm’):

 

def LD32_v1 : Instr<... “LD32” ...>,  Requires<[isV1]>;

def LD32_v2 : Instr<... “LD.32” ...>, Requires<[isV2]>;

 

This all works fine, but there is a large number of them which makes maintenance
difficult.  This also adds to the burden of selection when using ‘BuildMI’ in
the C++ code, as I have to do things like:

 

if (isV1())

  BuildMI(..., TII->get(SHAVE::LD32_v1)

else if (isV2())

  BuildMI(..., TII->get(SHAVE::LD32_v2)

 

What I would like, is for some mechanism that can substitute the version
specific mnemonic dynamically (perhaps using a lookup table), and I could reduce
the above to just:

 

def LD32 : Instr<... “??MetaMnemonic??” ...>;

and:

BuildMI(..., TII->get(SHAVE::LD32)

 

Does anyone know how this can be achieved without resort to placing some
Meta-Mnemonic for ‘??MetaMnemonic??’ and replacing this with the version
specific value during AsmPrinting?

 

Some instructions have more elaborate substitutions, but the general principle
is the same and there are a large number of instructions that are affected which
makes the TD files very large, and the conditional ‘BuildMI’ code
overcomplicated.

 

Thanks,

 

            MartinO

 


_______________________________________________
LLVM Developers mailing list
llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> 
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

 

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Simon Dardis via llvm-dev

2016-Jul-08 12:31 UTC

head link

[llvm-dev] Dynamic selection of assembly mnemonic strings

One possible approach is to use the instruction mapping infrastructure: 
http://llvm.org/docs/HowToUseInstrMappings.html

This provides a simple 1:1 mapping between the same instruction in two ISAs. For
MIPS we use this to map the base MIPS ISA
to the microMIPS ISA, and allows us to write the bulk of our .cpp files without
multiple switches on ISA.

Thanks,
Simon

From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Martin
J. O'Riordan via llvm-dev
Sent: 08 July 2016 12:58
To: 'Bruce Hoult'
Cc: 'LLVM Developers'
Subject: Re: [llvm-dev] Dynamic selection of assembly mnemonic strings

Thanks for the quick answer Bruce.

So far as I can tell (from a quick read), this is really for integrated
assemblers/disassemblers - but we use an external assembler.  When invoking
clang we would provide ‘-mcpu=chip_v1’ or ‘-mcpu=chip_v2’, and the mnemonic
‘LD32’ is only valid when compiling for ‘chip_v1’, while ‘LD.32’ is only valid
when compiling for ‘chip_v2’.  But I will study the mnemonic aliasing carefully
to see if it does provide what I need.

All the best,

            MartinO

From: bruce.hoult at gmail.com<mailto:bruce.hoult at gmail.com>
[mailto:bruce.hoult at gmail.com] On Behalf Of Bruce Hoult
Sent: 08 July 2016 12:32
To: Martin J. O'Riordan <Martin.ORiordan at
movidius.com<mailto:Martin.ORiordan at movidius.com>>
Cc: LLVM Developers <llvm-dev at lists.llvm.org<mailto:llvm-dev at
lists.llvm.org>>
Subject: Re: [llvm-dev] Dynamic selection of assembly mnemonic strings

Do instruction aliases do the job?

http://llvm.org/docs/CodeGenerator.html#instruction-alias-processing

Is it ok to have the same source file use LD32 in one instruction but LD.32 in
the next one, or do you want different modes?


On Fri, Jul 8, 2016 at 2:24 PM, Martin J. O'Riordan via llvm-dev
<llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>>
wrote:
Hi LLVM Dev,

I have an old problem that I’ve wanted to clean-up for some time.  Our chip has
gone through a number of iterations in the past few years, but with each
revision there have been changes to some of the mnemonics for instructions. 
These are mostly very simple, for example we had a 32-bit load from memory
instruction named ‘LD32’ in one version of the chip, but for a later version
this was changed to ‘LD.32’.

The semantics and schedule remained the same, but in the TD file I had to
introduce two ‘def’s for this (actually, I abstract a bit more and use a
‘defm’):

def LD32_v1 : Instr<... “LD32” ...>,  Requires<[isV1]>;
def LD32_v2 : Instr<... “LD.32” ...>, Requires<[isV2]>;

This all works fine, but there is a large number of them which makes maintenance
difficult.  This also adds to the burden of selection when using ‘BuildMI’ in
the C++ code, as I have to do things like:

if (isV1())
  BuildMI(..., TII->get(SHAVE::LD32_v1)
else if (isV2())
  BuildMI(..., TII->get(SHAVE::LD32_v2)

What I would like, is for some mechanism that can substitute the version
specific mnemonic dynamically (perhaps using a lookup table), and I could reduce
the above to just:

def LD32 : Instr<... “??MetaMnemonic??” ...>;
and:
BuildMI(..., TII->get(SHAVE::LD32)

Does anyone know how this can be achieved without resort to placing some
Meta-Mnemonic for ‘??MetaMnemonic??’ and replacing this with the version
specific value during AsmPrinting?

Some instructions have more elaborate substitutions, but the general principle
is the same and there are a large number of instructions that are affected which
makes the TD files very large, and the conditional ‘BuildMI’ code
overcomplicated.

Thanks,

            MartinO


_______________________________________________
LLVM Developers mailing list
llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

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Martin J. O'Riordan via llvm-dev

2016-Jul-08 12:52 UTC

head link

[llvm-dev] Dynamic selection of assembly mnemonic strings

This looks promising Simon.  And there are aspects of the ‘InstAlias’ class that
may be useful too.  Also, your reference to its use in the MIPS implementation
will help me to learn by example.

 

Thanks very much for your insights,

 

            MartinO

 

From: Simon Dardis [mailto:Simon.Dardis at imgtec.com] 
Sent: 08 July 2016 13:31
To: Martin.ORiordan at Movidius.com
Cc: llvm-dev at lists.llvm.org
Subject: RE: [llvm-dev] Dynamic selection of assembly mnemonic strings

 

One possible approach is to use the instruction mapping infrastructure: 
http://llvm.org/docs/HowToUseInstrMappings.html

 

This provides a simple 1:1 mapping between the same instruction in two ISAs. For
MIPS we use this to map the base MIPS ISA

to the microMIPS ISA, and allows us to write the bulk of our .cpp files without
multiple switches on ISA.

 

Thanks,

Simon

 

From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Martin
J. O'Riordan via llvm-dev
Sent: 08 July 2016 12:58
To: 'Bruce Hoult'
Cc: 'LLVM Developers'
Subject: Re: [llvm-dev] Dynamic selection of assembly mnemonic strings

 

Thanks for the quick answer Bruce.

 

So far as I can tell (from a quick read), this is really for integrated
assemblers/disassemblers - but we use an external assembler.  When invoking
clang we would provide ‘-mcpu=chip_v1’ or ‘-mcpu=chip_v2’, and the mnemonic
‘LD32’ is only valid when compiling for ‘chip_v1’, while ‘LD.32’ is only valid
when compiling for ‘chip_v2’.  But I will study the mnemonic aliasing carefully
to see if it does provide what I need.

 

All the best,

 

            MartinO

 

From: bruce.hoult at gmail.com <mailto:bruce.hoult at gmail.com> 
[mailto:bruce.hoult at gmail.com] On Behalf Of Bruce Hoult
Sent: 08 July 2016 12:32
To: Martin J. O'Riordan <Martin.ORiordan at movidius.com
<mailto:Martin.ORiordan at movidius.com> >
Cc: LLVM Developers <llvm-dev at lists.llvm.org <mailto:llvm-dev at
lists.llvm.org> >
Subject: Re: [llvm-dev] Dynamic selection of assembly mnemonic strings

 

Do instruction aliases do the job?

 

http://llvm.org/docs/CodeGenerator.html#instruction-alias-processing

 

Is it ok to have the same source file use LD32 in one instruction but LD.32 in
the next one, or do you want different modes?

 

 

On Fri, Jul 8, 2016 at 2:24 PM, Martin J. O'Riordan via llvm-dev
<llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> >
wrote:

Hi LLVM Dev,

 

I have an old problem that I’ve wanted to clean-up for some time.  Our chip has
gone through a number of iterations in the past few years, but with each
revision there have been changes to some of the mnemonics for instructions. 
These are mostly very simple, for example we had a 32-bit load from memory
instruction named ‘LD32’ in one version of the chip, but for a later version
this was changed to ‘LD.32’.

 

The semantics and schedule remained the same, but in the TD file I had to
introduce two ‘def’s for this (actually, I abstract a bit more and use a
‘defm’):

 

def LD32_v1 : Instr<... “LD32” ...>,  Requires<[isV1]>;

def LD32_v2 : Instr<... “LD.32” ...>, Requires<[isV2]>;

 

This all works fine, but there is a large number of them which makes maintenance
difficult.  This also adds to the burden of selection when using ‘BuildMI’ in
the C++ code, as I have to do things like:

 

if (isV1())

  BuildMI(..., TII->get(SHAVE::LD32_v1)

else if (isV2())

  BuildMI(..., TII->get(SHAVE::LD32_v2)

 

What I would like, is for some mechanism that can substitute the version
specific mnemonic dynamically (perhaps using a lookup table), and I could reduce
the above to just:

 

def LD32 : Instr<... “??MetaMnemonic??” ...>;

and:

BuildMI(..., TII->get(SHAVE::LD32)

 

Does anyone know how this can be achieved without resort to placing some
Meta-Mnemonic for ‘??MetaMnemonic??’ and replacing this with the version
specific value during AsmPrinting?

 

Some instructions have more elaborate substitutions, but the general principle
is the same and there are a large number of instructions that are affected which
makes the TD files very large, and the conditional ‘BuildMI’ code
overcomplicated.

 

Thanks,

 

            MartinO

 


_______________________________________________
LLVM Developers mailing list
llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> 
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

 

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llvm dev - Jul 2016 - Dynamic selection of assembly mnemonic strings

[llvm-dev] Dynamic selection of assembly mnemonic strings

[llvm-dev] Dynamic selection of assembly mnemonic strings

[llvm-dev] Dynamic selection of assembly mnemonic strings