Hi all,
I'm trying to continue an existing m68k backend for LLVM. I'm completely
new
to LLVM development so I've been muddling my way through mostly by trial and
error and using existing back ends for reference. I'm trying to implement
code to allow calling. I am compiling this C code --
typedef unsigned int uint32_t;
typedef char int8_t;
uint32_t foo(uint32_t x, int8_t y)
{
return (x | (1 << 17)) + y;
}
int main()
{
uint32_t b = foo(10,12);
}
And getting the following error from LLVM --
# Machine code for function main: Post SSA
Frame Objects:
fi#0: size=4, align=4, at location [SP]
Function Live Outs: %D0L
BB#0: derived from LLVM BB %entry
ADJCALLSTACKDOWN 6, %A7<imp-def>, %A7<imp-use>
%vreg2<def> = COPY %A7; DR32:%vreg2
%vreg1<def> = COPY %vreg2; AR:%vreg1 DR32:%vreg2
MOVElim %vreg1<kill>, 0, 10; mem:ST4[<unknown>](align=2)
AR:%vreg1
%vreg2<def,tied1> = ADDlqd %vreg2<tied0>, 4,
%CCR<imp-def,dead>;
DR32:%vreg2
%vreg3<def> = COPY %vreg2; AR:%vreg3 DR32:%vreg2
MOVEbim %vreg3<kill>, 0, 12; mem:ST1[<unknown>] AR:%vreg3
CALL <ga:@foo>, %A7<imp-use>, ...
ADJCALLSTACKUP 6, 0, %A7<imp-def>, %A7<imp-use>
%vreg4<def> = COPY %D0L; DR32:%vreg4
MOVEldm <fi#0>, 0, %vreg4<kill>; mem:ST4[%b] DR32:%vreg4
%vreg5<def> = MOVEQ 0; DR32:%vreg5
%D0L<def> = COPY %vreg5<kill>; DR32:%vreg5
RTS %D0L<imp-use,kill>
# End machine code for function main.
*** Bad machine code: Using an undefined physical register ***
- function: main
- basic block: BB#0 entry (0xa19eac)
- instruction: %vreg4<def> = COPY %D0L; DR32:%vreg4
- operand 1: %D0L
LLVM ERROR: Found 1 machine code errors.
Stack dump:
0. Program arguments:
D:\RetroMods\Jaguar\Compiler\llvm-build\bin\Debug\llc
.exe -mtriple m68k-apple-mac test.ll
1. Running pass 'Function Pass Manager' on module
'test.ll'.
2. Running pass 'Greedy Register Allocator' on function
'@main'
To me this looks like the result from the call (D0) is not being set
somewhere to let LLVM know the register is available when it tries to copy
it into the virtual register. I'm using the MSP430 target as reference, and
I'm doing everything this target is, so I'm not sure what I'm
missing.
Any tips would be most appreciated.
On 7/8/2015 11:40 AM, James Boulton wrote:> > Function Live Outs: %D0L >Live outs? How old are your sources? See this: commit e6dc59891fc53d65b3f6d19772d26e23e0cc1cac Author: Jakob Stoklund Olesen <stoklund at 2pi.dk> Date: Tue Feb 5 18:21:56 2013 +0000 Remove liveout lists from MachineRegisterInfo. All targets are now adding return value registers as implicit uses on return instructions, and there is no longer a need for the live out lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk at 174417 91177308-0d3 -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On 7/8/2015 11:40 AM, James Boulton wrote:> > CALL <ga:@foo>, %A7<imp-use>, ... > > To me this looks like the result from the call (D0) is not being set > somewhere to let LLVM know the register is available when it tries to copy > it into the virtual register. I'm using the MSP430 target as reference, and > I'm doing everything this target is, so I'm not sure what I'm missing. > > Any tips would be most appreciated.The CALL instruction should have an implicit def of the register used to return a value. -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Quite old -- I'm working with 3.2 at the moment as that's what the code I am basing my work off is built with at the moment. I plan to try and add some functionality and then update to 3.6 when I understand more. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Krzysztof Parzyszek Sent: 08 July 2015 17:53 To: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] New backend help request. On 7/8/2015 11:40 AM, James Boulton wrote:> > Function Live Outs: %D0L >Live outs? How old are your sources? See this: commit e6dc59891fc53d65b3f6d19772d26e23e0cc1cac Author: Jakob Stoklund Olesen <stoklund at 2pi.dk> Date: Tue Feb 5 18:21:56 2013 +0000 Remove liveout lists from MachineRegisterInfo. All targets are now adding return value registers as implicit uses on return instructions, and there is no longer a need for the live out lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk at 174417 91177308-0d3 -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ LLVM Developers mailing list LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
I'm trying to figure out how to map more complex CISC instructions now. For example on the 68000, you have things like -- add.w (a0)+,(a1)+ So that equates to: temp1 = load a0 add 2, a0 temp2 = load a1 temp1 = add temp1, temp2 store temp1, a1 add 2, a1 How do I express that in a form for LLVM? I see things like pre_store and post_store, but I cant find anything in the way of documentation about this. And there doesn't appear to be a pre_load and post_load matching pair or anything like that... Thanks!