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...crements the pointer > value after the move. We have Instruction format and pattern for this > type of instructions. > > How to encode the information that the pointer is incremented? As you seem to be aware, LLVM has patterns specifically to match pre/post increment loads and stores (post_store). In your *ISelLowering.cpp file, you'll need to call setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same for setIndexedStoreAction. Then you'll need to implement a getPostIndexedAddressParts function in that same file (you can look in the ARM backend for an example). If...

Hi, We have an architecture where the indirect move instruction implicitly increments the pointer value after the move. We have Instruction format and pattern for this type of instructions. How to encode the information that the pointer is incremented? Thanks and regards, Shashidhar

...r >> value after the move. We have Instruction format and pattern for this >> type of instructions. >> >> How to encode the information that the pointer is incremented? > As you seem to be aware, LLVM has patterns specifically to match pre/post increment loads and stores (post_store). In your *ISelLowering.cpp file, you'll need to call setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same for setIndexedStoreAction. Then you'll need to implement a getPostIndexedAddressParts function in that same file (you can look in the ARM backend for an example). If...

...truction format and pattern for > >> this > >> type of instructions. > >> > >> How to encode the information that the pointer is incremented? > > As you seem to be aware, LLVM has patterns specifically to match > > pre/post increment loads and stores (post_store). In your > > *ISelLowering.cpp file, you'll need to call > > setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same > > for setIndexedStoreAction. Then you'll need to implement a > > getPostIndexedAddressParts function in that same file (you can &gt...

...d pattern for >>>> this >>>> type of instructions. >>>> >>>> How to encode the information that the pointer is incremented? >>> As you seem to be aware, LLVM has patterns specifically to match >>> pre/post increment loads and stores (post_store). In your >>> *ISelLowering.cpp file, you'll need to call >>> setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same >>> for setIndexedStoreAction. Then you'll need to implement a >>> getPostIndexedAddressParts function in that same file...

What about things like pre_store and post_store, though? If there was a pre_load and post_load this would largely solve the problem. Of course there are a wealth of addressing modes for the 68k, but they should be able to be dealt with like this I think? -----Original Message----- From: Dr D. Chisnall [mailto:dc552 at hermes.cam.ac.uk] On Beh...

...map more complex CISC instructions now. For example on the 68000, you have things like -- add.w (a0)+,(a1)+ So that equates to: temp1 = load a0 add 2, a0 temp2 = load a1 temp1 = add temp1, temp2 store temp1, a1 add 2, a1 How do I express that in a form for LLVM? I see things like pre_store and post_store, but I cant find anything in the way of documentation about this. And there doesn't appear to be a pre_load and post_load matching pair or anything like that... Thanks!

Hi all, I'm trying to continue an existing m68k backend for LLVM. I'm completely new to LLVM development so I've been muddling my way through mostly by trial and error and using existing back ends for reference. I'm trying to implement code to allow calling. I am compiling this C code -- typedef unsigned int uint32_t; typedef char int8_t; uint32_t foo(uint32_t x, int8_t y) {