Displaying 2 results from an estimated 2 matches for "xi64".
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2014 Apr 22
2
[LLVMdev] where is F7 opcode for TEST instruction on X86?
...lt;0x84, "test", Xi8 , X86testpat, MRMSrcReg>;
def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>;
def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>;
def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>;
} // isCommutable
def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>;
def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>;
def...
2018 Mar 28
1
Taking over an x86 opcode for my own instruction
...39;m getting errors of the form:
Error: Primary decode conflict: TEST64ri32 would overwrite
CACHE_OPERAND_B64i
ModRM 199
Opcode 247
Context IC_64BIT_REXW
When I look at the definition of TEST64ri32, I see:
let Predicates = [In64BitMode] in
def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
It looks like TEST64ri32 is using opcode 0xF6 -- why is there a conflict
with 0xF1?
Even if I comment out TEST64ri32 (which I recognize is not a good idea), I
still get a similar error:
Error: Primary decode conflict: NOT64r would overwrite CACHE_OPERAND_B64i
ModRM 215...