Hi all. if there is limitation for the registers to be used together in an instruction, should i try to change it in the register allocation pass or should i try it somewhere else?? example. lets say we have to add 2 registers addu rx ,ry ,rz there is a limitation that says that the two regs that will be added they can not have the same mod4 so we can add r1 , r2 but cannot add r1,r5. thanks Stavropoulos Nikos -- View this message in context: http://llvm.1065342.n5.nabble.com/Register-allocation-limitations-tp62967.html Sent from the LLVM - Dev mailing list archive at Nabble.com.
Hi Nikos, You can model your requirement in the *.td using RegisterClass as def SrcRegs : RegisterClass<"Src", [i32], 4, (add R0, R2, R4, R6 )>; def DstRegs : RegisterClass<"Dst", [i32], 4, (add R1, R3, R5, R7 )>; Thanks ~Umesh On Thu, Nov 7, 2013 at 8:25 PM, Stavropoulos Nikos < n.stavropoulos at think-silicon.com> wrote:> Hi all. > > if there is limitation for the registers to be used together in an > instruction, should i try to change it in the register allocation pass > or should i try it somewhere else?? > > example. > > lets say we have to add 2 registers > > addu rx ,ry ,rz > > there is a limitation that says that the two regs that will be added they > can not have the same mod4 > so we can add r1 , r2 but cannot add r1,r5. > > > thanks > Stavropoulos Nikos > > > > > -- > View this message in context: > http://llvm.1065342.n5.nabble.com/Register-allocation-limitations-tp62967.html > Sent from the LLVM - Dev mailing list archive at Nabble.com. > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131107/771eb834/attachment.html>
Hi Umesh, thanks for answering. i think i did not describe the problem well enough. i have no problem with the register that should be written. lets say we have a madd instruction madd D, R, S, T. D : don't care R : lets say it is R4 S : should be whatever register that has different mod(register,4) != 0 so lets pick R7 T: should be whatever register that has different mod(register,4) != 0 (because of R) and should be whatever register that has different mod(register,4) != 3 (because of S) so we have to pick someone with mod 1 or 2 so we can choose R5 is there a way to do it somehow without declaring different register classes, some dynamic kind way? -- View this message in context: http://llvm.1065342.n5.nabble.com/Register-allocation-limitations-tp62967p62991.html Sent from the LLVM - Dev mailing list archive at Nabble.com.