Displaying 2 results from an estimated 2 matches for "tp62967p62991".
2013 Nov 07
0
[LLVMdev] Register allocation limitations
Hi Nikos,
You can model your requirement in the *.td using RegisterClass as
def SrcRegs : RegisterClass<"Src", [i32], 4,
(add R0, R2, R4, R6
)>;
def DstRegs : RegisterClass<"Dst", [i32], 4,
(add R1, R3, R5, R7
)>;
Thanks
~Umesh
On Thu, Nov 7, 2013 at 8:25 PM, Stavropoulos Nikos <
n.stavropoulos at think-silicon.com> wrote:
> Hi all.
2013 Nov 07
2
[LLVMdev] Register allocation limitations
Hi all.
if there is limitation for the registers to be used together in an
instruction, should i try to change it in the register allocation pass
or should i try it somewhere else??
example.
lets say we have to add 2 registers
addu rx ,ry ,rz
there is a limitation that says that the two regs that will be added they
can not have the same mod4
so we can add r1 , r2 but cannot add r1,r5.