llvm dev - Feb 2013 - [LLVMdev] How to set isTarget bit for a complex intrinsic class in tblgen?

Dear all,

Let's say there is some complex tblgen intrinsic definition, for example:

class MEMBAR<string StrOp, Intrinsic IntOP> :
              NVPTXInst<(outs), (ins),
            StrOp, [(IntOP)]>;

def INT_MEMBAR_CTA : MEMBAR<"membar.cta;", int_nvvm_membar_cta>;
def INT_MEMBAR_GL  : MEMBAR<"membar.gl;",  int_nvvm_membar_gl>;
def INT_MEMBAR_SYS : MEMBAR<"membar.sys;", int_nvvm_membar_sys>;

Question: how to set an isTarget bit to the Intrinsic subclass of it?

In simple cases that would be

let isTarget = 1 in { ... }

How to make the same here?

Thanks,
- D.
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One possibility is to derive a subclass and set isTarget to 1 in it and use
that class. e.g.

class MyMEMBAR<...> : MEMBAR<...> {
 let isTarget = 1;
}

-- Sean Silva
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