llvm dev - Oct 2012 - [LLVMdev] Proposed SelectionDAGBuilder patch - load serialisation

I posted to llvmdev a few months ago to ask for advice on the best way to avoid
the SelectionDAGBuilder from imposing a constraint whereby a volatile load would
be serialised relative to all pending loads. The LLVM LRM says that a volatile
load only needs to be serialised relative to other volatile loads and, while it
may not matter to most targets, the current behaviour of the SelectionDAGBuilder
makes a big difference to the HCS12 target that I've been working on because
it prevents selection of efficient instruction sequences in some cases (see
postings on llvmdev starting 13 August 2012 for details).

I've never produced a patch before and I'm not yet that familiar with
LLVM so please forgive me if that attached patch isn't up to the required
standard. If anyone could suggest a neater way of achieving the same effect
I'd be happy to rewrite it.

I've also produced a regression test for the MSP430 target, as it's the
closest to the HCS12 microcontroller which I'm targetting.

I've run the regression tests with the patch applied and also run the
nightly test. Both of them pass.

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