Displaying 3 results from an estimated 3 matches for "hcs12".
2012 Oct 30
0
[LLVMdev] Proposed SelectionDAGBuilder patch - load serialisation
...whereby a volatile load would be serialised relative to all pending loads. The LLVM LRM says that a volatile load only needs to be serialised relative to other volatile loads and, while it may not matter to most targets, the current behaviour of the SelectionDAGBuilder
makes a big difference to the HCS12 target that I've been working on because it prevents selection of efficient instruction sequences in some cases (see postings on llvmdev starting 13 August 2012 for details).
I've never produced a patch before and I'm not yet that familiar with LLVM so please forgive me if that attache...
2011 Oct 14
0
[LLVMdev] Native MCAsmStreamer?
...icrocontroller, in the process of
learning the LLVM backend things.
It's going well so far, but I have a question:
I'd like to use a pure MCAsmStreamer and not have another layer of glue.
Right now, I have the following to make it compile:
---
using namespace llvm;
namespace {
class HCS12AsmPrinter : public AsmPrinter {
public:
HCS12AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
: AsmPrinter(TM, Streamer) {}
virtual const char *getPassName() const {
return "HCS12 Assembly Printer";
}
};
} // end of anonymous namespace
// Fo...
2014 Jul 05
6
[LLVMdev] Instructions on a target with no general purpose registers
I've mentioned my sneaky plans to target the MOS6502 here before.
The big issue I think is that a lot of instructions don't really have a choice for output register. It all just goes into the accumulator, X index, or Y index based on the specific instruction.
So, my question is, when I'm defining my ins, outs and registers for these instructions, is it going to be a problem that