Displaying 14 results from an estimated 14 matches for "memoryvt".
2011 Dec 12
3
[LLVMdev] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading
Hi all. The question about 'load' instruction.
When we promote
v2i5 = load <addr> ; <MemoryVT = v2i5>
to
v2i64 = load <addr> ;<MemoryVT = v2i5>
should we insert vector shuffling that moves second v2i5 item to the
second v2i64 item?
Or it is still depends from target?
Thanks.
-Stepan.
2011 Dec 13
3
[LLVMdev] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading
Yes. It doesn't works properly. I also read the your discussion in bug
1784: http://llvm.org/bugs/show_bug.cgi?id=1784
I found that know Type and Vector Lagalization and in DAGCombining
implicitly assumed that element size of MemoryVT is multiply of 8 bits.
Thats the main reason why v2i5 works improperly with load/store. But I
can't determine exactly what MemoryVT means...
-Stepan.
Stepan Dyatkovskiy wrote:
> Probably, I misunderstood MemoryVT purpose? Should it be a type that
> equal to original vector type (e.g....
2011 Dec 13
0
[LLVMdev] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading
Probably, I misunderstood MemoryVT purpose? Should it be a type that
equal to original vector type (e.g. v2i5). Or it is a type of memory
area for this vector (e.g. v2i8) ?
-Stepan.
Stepan Dyatkovskiy wrote:
> Hi all. The question about 'load' instruction.
> When we promote
> v2i5 = load<addr> ;<Memory...
2011 Dec 13
0
[LLVMdev] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading
Hi Stepan,
> Yes. It doesn't works properly. I also read the your discussion in bug 1784:
> http://llvm.org/bugs/show_bug.cgi?id=1784
> I found that know Type and Vector Lagalization and in DAGCombining implicitly
> assumed that element size of MemoryVT is multiply of 8 bits. Thats the main
> reason why v2i5 works improperly with load/store. But I can't determine exactly
> what MemoryVT means...
do you understand what it means in the non-vector case?
Ciao, Duncan.
>
> -Stepan.
>
> Stepan Dyatkovskiy wrote:
>> Probabl...
2009 Jul 31
4
[LLVMdev] RFC: SDNode Flags
...mark instructions where movnt (on x86) and other goodness
can happen (we'll also add the TableGen patterns to properly select movnt).
In our tree we simply added another flag to the MemSDNode constructor
and embedded it in SubclassData:
MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT,
const Value *srcValue, int SVOff,
unsigned alignment, bool isvolatile, bool NonTemporal);
This is ugly for a variety of reasons and also doesn't scale as we
want to add more of this kind of information.
So what if we replace Volatile/NonTemporal with a single bitvecto...
2011 Dec 13
3
[LLVMdev] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading
Please ignore my concurrent post :-) Lets proceed in this branch.
> do you understand what it means in the non-vector case?
I'm beginning to understand it now. It means the type that should be in
abstract VM memory. Isn't it? The main question about MemoryVT is:
should it be original always (as it was defined in .ll) or not?
About vectors with element size less than 8 bits. This topic is
interesting for me. I would like to work with it. What is the best place
for discussing? llvmdev or bug #1784 (vectors of i1 and vectors x86 long
double don't...
2009 Aug 01
0
[LLVMdev] RFC: SDNode Flags
...nd other
> goodness
> can happen (we'll also add the TableGen patterns to properly select
> movnt).
>
> In our tree we simply added another flag to the MemSDNode constructor
> and embedded it in SubclassData:
>
> MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT,
> const Value *srcValue, int SVOff,
> unsigned alignment, bool isvolatile, bool NonTemporal);
>
> This is ugly for a variety of reasons and also doesn't scale as we
> want to add more of this kind of information.
>
> So what if we replace Volatile/Non...
2009 Aug 03
0
[LLVMdev] RFC: SDNode Flags
...nd other
> goodness
> can happen (we'll also add the TableGen patterns to properly select
> movnt).
>
> In our tree we simply added another flag to the MemSDNode constructor
> and embedded it in SubclassData:
>
> MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT,
> const Value *srcValue, int SVOff,
> unsigned alignment, bool isvolatile, bool NonTemporal);
>
> This is ugly for a variety of reasons and also doesn't scale as we
> want to add more of this kind of information.
>
> So what if we replace Volatile/Non...
2011 Dec 13
0
[LLVMdev] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading
...vskiy wrote:
> Please ignore my concurrent post :-) Lets proceed in this branch.
>
>> do you understand what it means in the non-vector case?
> I'm beginning to understand it now. It means the type that should be in
> abstract VM memory. Isn't it? The main question about MemoryVT is:
> should it be original always (as it was defined in .ll) or not?
>
> About vectors with element size less than 8 bits. This topic is
> interesting for me. I would like to work with it. What is the best place
> for discussing? llvmdev or bug #1784 (vectors of i1 and vectors x...
2011 Dec 14
1
[LLVMdev] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading
...vskiy wrote:
> Please ignore my concurrent post :-) Lets proceed in this branch.
>
>> do you understand what it means in the non-vector case?
> I'm beginning to understand it now. It means the type that should be in
> abstract VM memory. Isn't it? The main question about MemoryVT is:
> should it be original always (as it was defined in .ll) or not?
>
> About vectors with element size less than 8 bits. This topic is
> interesting for me. I would like to work with it. What is the best place
> for discussing? llvmdev or bug #1784 (vectors of i1 and vectors x...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...AG.getNode(ISD::RET, dl, MVT::Other,
- &NewValues[0], NewValues.size());
+ Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
break;
}
}
@@ -2618,8 +2201,7 @@
}
}
- switch (getTypeAction(ST->getMemoryVT())) {
- case Legal: {
+ {
Tmp3 = LegalizeOp(ST->getValue());
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
ST->getOffset());
@@ -2653,111 +2235,8 @@
}
break;
}
- case Promote:
-...
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
...vm/CodeGen/SelectionDAGNodes.h
index 072b6af..eac3eec 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -974,6 +974,7 @@ public:
/// Abstact virtual class for operations for memory operations
class MemSDNode : public SDNode {
private:
+
// MemoryVT - VT of in-memory value.
EVT MemoryVT;
@@ -1013,9 +1014,11 @@ public:
bool isNonTemporal() const { return (SubclassData >> 6) & 1; }
bool isInvariant() const { return (SubclassData >> 7) & 1; }
+
AtomicOrdering getOrdering() const {
return AtomicOrdering((Su...