Displaying 2 results from an estimated 2 matches for "vextract".
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extract
2011 Mar 31
3
[LLVMdev] Assert in VerifySDNode
...am generating.
What I generate has worked fine from LLVM version 2.4 until now without causing any issues.
This is occuring while I am attempting to lower a vector extract elt to a custom SDNode that my backend understands.
I am creating the instruction like as follows:
Op = DAG.getNode(AMDILISD::VEXTRACT,
Op.getDebugLoc(), Op.getValueType(),
Op.getOperand(0),
DAG.getTargetConstant(dyn_cast<ConstantSDNode>(Op.getOperand(1)->getZExtValue() + 1), MVT::i32));
The custom backend instruction is defined as follows:
def SDTIL_GenVecExtract : SDTypeProfile<1, 2, [
SD...
2016 Aug 02
2
Instruction selection problems due to SelectionDAGBuilder
...i64 %vreg209, Constant:i64<0>
t85: ch = TokenFactor t41, t81, t83
t86: ch = br t85, BasicBlock:ch<vector.body25 0x1bd35f0>
I am curious what is wrong - I've tried to match the Mips' back end: I have put most
of the vector splat instructions and the vextract and INSERT_D_DESC instruction, etc .
I also don't get enough DEBUG information to understand where exactly the problem
comes from (probably I missed some TableGen record).
Please let me know if you have any idea.
Thank you very much,
Alex