llvm dev - Jan 2011 - [LLVMdev] How to avoid register reuse in machine instructions?

Is there a way to force the register allocator to avoid reusing an 
operand register for a definition?  For example, the following machine 
instruction reuses a register for the first operand and definition:

%uI7<def> = eq at III %uI7<kill>, %uI4

I'd like:

%uI8<def> = eq at III %uI7<kill>, %uI4

I'm guessing that the right way to do this would be to kill the operand 
registers after the given machine instruction rather than before it, but 
I don't see a way to mark it this way.

Andrew

Hello,
> I'm guessing that the right way to do this would be to kill the operand
> registers after the given machine instruction rather than before it, but
> I don't see a way to mark it this way.
Right now the only way is to mark output reg as earlyclobber (see ARM
backend for examples).
Note that post-RA scheduler is not yet aware about earlyclobber
operands and thus can break the constraint.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

On 01/19/2011 01:14 PM, Anton Korobeynikov wrote:
> Right now the only way is to mark output reg as earlyclobber (see ARM
> backend for examples).
> Note that post-RA scheduler is not yet aware about earlyclobber
> operands and thus can break the constraint.
>
That solved it, thank you!