llvm dev - Sep 2010 - [LLVMdev] [LLVMDev] [Modeling] About the structure of my allocator

I need to model my registers for my allocator. I need to identify the
super-register and the sub-register conflicts. Something like:

For each set of registers R in the set of aligned registers defined by the
input request virtual register alpha. Now each register block r in R can
have zero, one, or more registers defined in the block started at the
aligned size and ending at the aligned size plus the request register
alpha's size. The final step is to weigh and choose a block to put alpha
into.

How do I model the registers R and register blocks r to obtain my desired
information?

- Thanks
- Jeff Kunkel
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Would I be correct in assuming that the alias set is defined as the
registers which may reside in the same space as the register? In other words
the register is either a super or sub register which holds the same physical
location in the register set?

Could someone please explain what the Alias set is if it is not what I
described above?

TargetRegisterInfo::getAliasSet( unsigned reg )

Thanks
Jeff Kunkel

On Thu, Sep 2, 2010 at 1:56 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote:
> I need to model my registers for my allocator. I need to identify the
> super-register and the sub-register conflicts. Something like:
>
> For each set of registers R in the set of aligned registers defined by the
> input request virtual register alpha. Now each register block r in R can
> have zero, one, or more registers defined in the block started at the
> aligned size and ending at the aligned size plus the request register
> alpha's size. The final step is to weigh and choose a block to put
alpha
> into.
>
> How do I model the registers R and register blocks r to obtain my desired
> information?
>
> - Thanks
> - Jeff Kunkel
>
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On Sep 2, 2010, at 1:57 PM, Jeff Kunkel wrote:
> Would I be correct in assuming that the alias set is defined as the
registers which may reside in the same space as the register?
Yes.
> In other words the register is either a super or sub register which holds
the same physical location in the register set?
No.
> Could someone please explain what the Alias set is if it is not what I
described above?
An alias overlaps the register in some way such that both cannot be used at the
same time. All sub-registers and all super-registers are aliases, but there may
be aliases that are neither.

It is very rare to have an alias that is not a sub or super.

> Would I be correct in assuming that the alias set is defined as the
> registers which may reside in the same space as the register? In other
words
> the register is either a super or sub register which holds the same
physical
> location in the register set?
No. Aliased stuff might easily be neither sub- nor superregister.
> Could someone please explain what the Alias set is if it is not what I
> described above?
Think about MMX regs and x87 ones.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

Thank you!

The pieces are starting to fall into place finally.

I need to track which MachineBasicBlocks branch into
other MachineBasicBlocks. How do I do it?

I see a MachineOperand can hold a MachineBasicBlock*. Does this mean the
instruction may branch to the MachineBasicBlock, or can it be something like
an object reference?

- Thanks,
Jeff Kunkel

On Thu, Sep 2, 2010 at 1:56 PM, Jeff Kunkel <jdkunk3 at gmail.com> wrote:
> I need to model my registers for my allocator. I need to identify the
> super-register and the sub-register conflicts. Something like:
>
> For each set of registers R in the set of aligned registers defined by the
> input request virtual register alpha. Now each register block r in R can
> have zero, one, or more registers defined in the block started at the
> aligned size and ending at the aligned size plus the request register
> alpha's size. The final step is to weigh and choose a block to put
alpha
> into.
>
> How do I model the registers R and register blocks r to obtain my desired
> information?
>
> - Thanks
> - Jeff Kunkel
>
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On Sep 2, 2010, at 2:44 PMPDT, Jeff Kunkel wrote:
> I need to track which MachineBasicBlocks branch into other  
> MachineBasicBlocks. How do I do it?
Look at the Predecessor/Successor lists, which are target-independent
> I see a MachineOperand can hold a MachineBasicBlock*. Does this mean  
> the instruction may branch to the MachineBasicBlock, or can it be  
> something like an object reference?
It can also be the dreaded gcc "address of label" extension.  Number  
and ordering of instruction operands is target-dependent.