llvm dev - Dec 2009 - [LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported

I have code that is generating sign extend in reg on a v8i32, but the
backend does not support this data type.  This then asserts in
LegalizeVectorTypes.cpp:389 because there is no function to split this
vector into smaller sizes. Would a correct solution be to add this case
so to trigger the SplitVecRes_BinaryOp function?

 

This asserts on both my backend and x86 and TOT does not seem to have
any code to handle this.

 

Thanks,

Micah

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On Wed, Dec 9, 2009 at 8:40 PM, Villmow, Micah <Micah.Villmow at amd.com>
wrote:
> I have code that is generating sign extend in reg on a v8i32, but the
> backend does not support this data type.  This then asserts in
> LegalizeVectorTypes.cpp:389 because there is no function to split this
> vector into smaller sizes. Would a correct solution be to add this case so
> to trigger the SplitVecRes_BinaryOp function?
SIGN_EXTEND_INREG isn't a binary operation; the correct expansion is
expanding the first operand the same way SplitVecRes_BinaryOp does,
while passing through the second operand untouched.  But yes, adding a
case to DAGTypeLegalizer::SplitVectorResult is the right idea.

If anyone else is curious, here's a testcase which crashes on x86 when
llc is run over it:
define <8 x i32> @a(<8 x i32> %a) {
  %b = trunc <8 x i32> %a to <8 x i16>
  %c = sext <8 x i16> %b to <8 x i32>
  ret <8 x i32> %c
}

-Eli

Thanks Eli,
 I'll see if I can get something working and submit a patch.


Micah

-----Original Message-----
From: Eli Friedman [mailto:eli.friedman at gmail.com] 
Sent: Wednesday, December 09, 2009 11:18 PM
To: Villmow, Micah
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] SplitVecRes with SIGN_EXTEND_INREG unsupported

On Wed, Dec 9, 2009 at 8:40 PM, Villmow, Micah <Micah.Villmow at amd.com>
wrote:
> I have code that is generating sign extend in reg on a v8i32, but the
> backend does not support this data type.  This then asserts in
> LegalizeVectorTypes.cpp:389 because there is no function to split this
> vector into smaller sizes. Would a correct solution be to add this case so
> to trigger the SplitVecRes_BinaryOp function?
SIGN_EXTEND_INREG isn't a binary operation; the correct expansion is
expanding the first operand the same way SplitVecRes_BinaryOp does,
while passing through the second operand untouched.  But yes, adding a
case to DAGTypeLegalizer::SplitVectorResult is the right idea.

If anyone else is curious, here's a testcase which crashes on x86 when
llc is run over it:
define <8 x i32> @a(<8 x i32> %a) {
  %b = trunc <8 x i32> %a to <8 x i16>
  %c = sext <8 x i16> %b to <8 x i32>
  ret <8 x i32> %c
}

-Eli