search for: dagtypelegalizer

Displaying 20 results from an estimated 116 matches for "dagtypelegalizer".

2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
> so I think we need to use non-extending load for element size less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly. > if (N->getOperand(0).getValueType().getVectorElementType().getSizeInBits() < 8) { > return DAG.getLoad(N->getValueType(0), dl, Store, StackPtr, MachinePointerInfo()); > } else { > return DAG.getExtLoad(ISD::EXTLOAD,...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...om] Sent: Saturday, September 16, 2017 00:38 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at gmail.com> Cc: llvm-dev at lists.llvm.org Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' Hi Elena, Thanks for your response. The store is ok but the extending load generates assertion after the store because MemVT is i8 and VT is i1 on following line. assert(MemVT.getScalarType().bitsLT(VT.getScalarType()) && "Should only be an exten...
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...licy... - Elena -----Original Message----- From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Friday, September 15, 2017 17:45 To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' Can someone give the comment about it please? Thanks, JinGu Kang On 14/09/17 12:05, jingu at codeplay.com wrote: > Hi All, > > I have a question about splitting 'EXTRACT_VECTOR_ELT' with 'v2i1'. I > have a llvm IR code sn...
2018 Mar 09
2
[SelectionDAG] DbgValue nodes aren't transferred
Hi, I have a problem that dbg_value nodes are not transferred when integer DAG nodes are promoted. For example, an i32 add node is promoted to a i64 add node by DAGTypeLegalizer::PromoteIntegerResult and its dbg_value node is not transferred to the new node. t9: i32 = add nsw t5, t8 --> t31: i64 = add t30, t7 ; the dbg_value node is not transferred to the new i64 add node. For expansion, DAGTypeLegalizer::SetExpandedInteger calls transferDbgValues() but I couldn...
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...11, setne:ch t16: i1 = extract_vector_elt t13, t15 t17: i32 = extract_vector_elt t8, t15 t18: i32 = extract_vector_elt t11, t15 t19: i1 = setcc t17, t18, setne:ch t20: i1 = xor t16, t19 ... I have not added any vector register class so 'DAGTypeLegalizer' tries to split the "t16: i1 = extract_vector_elt t13, t15" because t13's result type is 'v2i1'. If the size of vector element is less than 8bit, 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT()' function extends the elements to 8bit and stores them on stack...
2018 Mar 09
0
[SelectionDAG] DbgValue nodes aren't transferred
+ Adrian, Joshua + Jonas, since he contributed the transferDbgValues change in DAGTypeLegalizer::SetExpandedInteger > On Mar 8, 2018, at 5:44 PM, Se Jong Oh via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > I have a problem that dbg_value nodes are not transferred when integer DAG nodes are promoted. For example, an i32 add node is promoted to a i64 add nod...
2018 Mar 13
2
[SelectionDAG] DbgValue nodes aren't transferred
...dev at lists.llvm.org; Jonas Devlieghere <jdevlieghere at apple.com>; Adrian Prantl <aprantl at apple.com>; pidgeot18 at gmail.com Subject: Re: [llvm-dev] [SelectionDAG] DbgValue nodes aren't transferred + Adrian, Joshua + Jonas, since he contributed the transferDbgValues change in DAGTypeLegalizer::SetExpandedInteger On Mar 8, 2018, at 5:44 PM, Se Jong Oh via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Hi, I have a problem that dbg_value nodes are not transferred when integer DAG nodes are promoted. For example, an i32 add node is promoted t...
2013 Mar 05
4
[LLVMdev] Vector splitting vs widening
...setcc 0x23467e0, 0x23469e0, 0x23436a0 [ID=0] Split node result: 0x2348620: v2f32 = extract_subvector 0x23435a0, 0x2346de0 [ID=0] Widen node result 0: 0x2348820: v2i1 = setcc 0x2346ee0, 0x2348620, 0x23436a0 [ID=0] llc: lib/CodeGen/SelectionDAG/LegalizeTypes.h:599: llvm::SDValue llvm::DAGTypeLegalizer::GetWidenedVector(llvm::SDValue): Assertion `WidenedOp.getNode() && "Operand wasn't widened?"' failed. The problem is essentially the following: there are no vector f32 types (yet), so the <v4i1> = setcc <v4f32> node needs to be split and scalarized. The opera...
2012 Aug 16
1
[LLVMdev] DAGTypeLegalizer::RemapValue failure
Hi, If you are familiar with LegalizeTypes I will be glad if you can help me with the following scenario. I'm debugging some ll test that fails with an assertion in "void DAGTypeLegalizer::RemapValue(SDValue &N)" because it does not expect that a remap to a new node exists. However looking at the code for a while this seems to be a valid case. I see that many times nodes are added to ReplacedValues map as a value when their NodeID is 0, and therefore they might become a Ne...
2016 Jan 25
1
Return value from TargetLowering::LowerOperation?
...umed only the first two of the above cases can >> happen because there we do: >> >> SDValue Res = LowerOperation(SDValue(N, 0), DAG); >> if (Res.getNode()) >> Results.push_back(Res); >> >> So, when LowerOperationWrapper is called from >> DAGTypeLegalizer::CustomLowerNode, and my target's LowerOperation >> returns the same SDValue as it was called on since we don't want to do >> anything special with this particular SDValue, then we get an assert >> "Potential legalization loop!" when DAGTypeLegalizer::CustomLower...
2016 Jan 22
3
Return value from TargetLowering::LowerOperation?
...e.g. in TargetLowering::LowerOperationWrapper, it seems like it is assumed only the first two of the above cases can happen because there we do: SDValue Res = LowerOperation(SDValue(N, 0), DAG); if (Res.getNode()) Results.push_back(Res); So, when LowerOperationWrapper is called from DAGTypeLegalizer::CustomLowerNode, and my target's LowerOperation returns the same SDValue as it was called on since we don't want to do anything special with this particular SDValue, then we get an assert "Potential legalization loop!" when DAGTypeLegalizer::CustomLowerNode tries to replace t...
2018 Mar 14
0
[SelectionDAG] DbgValue nodes aren't transferred
...; Jonas Devlieghere <jdevlieghere at apple.com>; Adrian Prantl <aprantl at apple.com>; pidgeot18 at gmail.com > Subject: Re: [llvm-dev] [SelectionDAG] DbgValue nodes aren't transferred > > + Adrian, Joshua > + Jonas, since he contributed the transferDbgValues change in DAGTypeLegalizer::SetExpandedInteger > > On Mar 8, 2018, at 5:44 PM, Se Jong Oh via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > Hi, > > I have a problem that dbg_value nodes are not transferred when integer DAG nodes are promoted. For exam...
2018 Mar 14
2
[SelectionDAG] DbgValue nodes aren't transferred
...t;; Adrian Prantl <aprantl at apple.com<mailto:aprantl at apple.com>>; pidgeot18 at gmail.com<mailto:pidgeot18 at gmail.com> Subject: Re: [llvm-dev] [SelectionDAG] DbgValue nodes aren't transferred + Adrian, Joshua + Jonas, since he contributed the transferDbgValues change in DAGTypeLegalizer::SetExpandedInteger On Mar 8, 2018, at 5:44 PM, Se Jong Oh via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Hi, I have a problem that dbg_value nodes are not transferred when integer DAG nodes are promoted. For example, an i32 add node is promoted t...
2013 Mar 05
0
[LLVMdev] Vector splitting vs widening
..., 0x23436a0 [ID=0] > > Split node result: 0x2348620: v2f32 = extract_subvector 0x23435a0, 0x2346de0 [ID=0] > > Widen node result 0: 0x2348820: v2i1 = setcc 0x2346ee0, 0x2348620, 0x23436a0 [ID=0] > > llc: lib/CodeGen/SelectionDAG/LegalizeTypes.h:599: llvm::SDValue llvm::DAGTypeLegalizer::GetWidenedVector(llvm::SDValue): Assertion `WidenedOp.getNode() && "Operand wasn't widened?"' failed. > > The problem is essentially the following: there are no vector f32 types (yet), so the <v4i1> = setcc <v4f32> node needs to be split and scalarized....
2012 Mar 23
2
[LLVMdev] Fixing VAARG on PPC64
...AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); > > setOperationAction(ISD::VAARG, MVT::i32, Promote); > > AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); > > but this does not seem to have any effect. I thought this would work > > because SDValue DAGTypeLegalizer::PromoteIntRes_VAARG seems to have > > the appropriate logic. Is this a bug, or am I misunderstanding how > > Promote works? > > IMHO, you are doing it right but it looks like ISD::VAARG is not > handled in SelectionDAGLegalize::PromoteNode() yet. DAGTypeLegalizer > is used...
2012 Mar 23
2
[LLVMdev] Fixing VAARG on PPC64
...ionAction(ISD::VAARG, MVT::i16, Promote); AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); setOperationAction(ISD::VAARG, MVT::i32, Promote); AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); but this does not seem to have any effect. I thought this would work because SDValue DAGTypeLegalizer::PromoteIntRes_VAARG seems to have the appropriate logic. Is this a bug, or am I misunderstanding how Promote works? Thanks again, Hal -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory
2010 Sep 22
2
[LLVMdev] r114523 (convert the last 4 X86ISD...) breaks clang
...:LowerSINT_TO_FP(llvm::SDValue, llvm::SelectionDAG&) const + 1017 10 clang 0x0000000100978b9b llvm::TargetLowering::LowerOperationWrapper(llvm::SDNode*, llvm::SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG&) const + 27 11 clang 0x00000001008d63e4 llvm::DAGTypeLegalizer::CustomLowerNode(llvm::SDNode*, llvm::EVT, bool) + 164 12 clang 0x00000001008cd718 llvm::DAGTypeLegalizer::ExpandIntegerOperand(llvm::SDNode*, unsigned int) + 280 13 clang 0x00000001008d290f llvm::DAGTypeLegalizer::run() + 991 14 clang 0x00000001008d87b8 llvm::Se...
2018 Mar 15
1
[SelectionDAG] DbgValue nodes aren't transferred
...; Jonas Devlieghere <jdevlieghere at apple.com>; Adrian Prantl <aprantl at apple.com>; pidgeot18 at gmail.com > Subject: Re: [llvm-dev] [SelectionDAG] DbgValue nodes aren't transferred > > + Adrian, Joshua > + Jonas, since he contributed the transferDbgValues change in DAGTypeLegalizer::SetExpandedInteger > > On Mar 8, 2018, at 5:44 PM, Se Jong Oh via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > I have a problem that dbg_value nodes are not transferred when integer DAG nodes are promoted. For example, an i32 add node is promoted to a i64...
2012 Mar 23
0
[LLVMdev] Fixing VAARG on PPC64
...16, Promote); > AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); > setOperationAction(ISD::VAARG, MVT::i32, Promote); > AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); > but this does not seem to have any effect. I thought this would work > because SDValue DAGTypeLegalizer::PromoteIntRes_VAARG seems to have the > appropriate logic. Is this a bug, or am I misunderstanding how Promote > works? IMHO, you are doing it right but it looks like ISD::VAARG is not handled in SelectionDAGLegalize::PromoteNode() yet. DAGTypeLegalizer is used to legalize "non-legal...
2012 Jan 11
1
[LLVMdev] widen_load fails on AVX
Hello Chris, We caught this failure: ./llc -mattr=+avx ../../test/CodeGen/X86/widen_load-2.ll llc: LegalizeTypes.cpp:831: void llvm::DAGTypeLegalizer::SetSplitVector(llvm::SDValue, llvm::SDValue, llvm::SDValue): Assertion `Lo.getValueType().getVectorElementType() == Op.getValueType().getVectorElementType() && 2*Lo.getValueType().getVectorNumElements() == Op.getValueType().getVectorNumElements() && Hi.getValueType() == Lo.getValue...