> If the condition is a vector of i1, then the value arguments must be
vectors of the same size, and the selection is done element by element.
> ...
> Note that the code generator does not yet support conditions with vector
type.
This issue seems to persist in the 2.6 prerelease. (It barfs in
instruction selection when there is a select with a vector condition.)
Is there any plan to support (or intention of supporting) vector
selects, now that they are representable in the IR?
It is a useful construct, and is useful to abstract across platforms
(e.g. SSE2/3 and SSE4.2 generally necessitate different strategies, as
do Cell SPU and AltiVec, and as will AVX, LRBni, ...), and at the very
least can be emulated by having a default lowering to the obvious per-
element extract-select-insert pattern.
For the time being, the workaround of using link-time selection of a
platform-specific intrinsic or library function is usable, but it
would be great to see it actually supported in the more common
backends, given that it was already deemed useful enough for inclusion
in the IR.
