search for: lrbni

..._rm; // Custom patterns sse1_binary_scalar_xs_node_rm; // Binary plus the rest of the sse1 "xs rm" classes, the mr encodings, all the binary operations, all the sse2 classes (which look like the sse1 classes except they use "xd", all the vector classes, all the AVX classes, LRBni, etc. We still have a combinatorial explosion problem. Of course, we only have to define the ones we actually use and that cuts down significantly on the numbers, but it's still large. So I'm still looking for a complete solution. Ideas welcome. -Dave

...cted :). The last thing missing for us now is AVX support in the JIT, but that is a different issue. However, there is one thing I do not fully understand: what if somebody actually wants a vector of 4 boolean values (i1) that should not be legalized to v4i32? For example, a code generator for LRBni would want to use the architecture's predicate registers for masks, in which case <16 x i1> should probably not be legalized to <16 x i32>, right? However, I reckon that native support of architectures with predicated execution is probably a bigger problem, anyway. Best, Ralf O...

...Is there any plan to support (or intention of supporting) vector selects, now that they are representable in the IR? It is a useful construct, and is useful to abstract across platforms (e.g. SSE2/3 and SSE4.2 generally necessitate different strategies, as do Cell SPU and AltiVec, and as will AVX, LRBni, ...), and at the very least can be emulated by having a default lowering to the obvious per- element extract-select-insert pattern. For the time being, the workaround of using link-time selection of a platform-specific intrinsic or library function is usable, but it would be great to see it actua...

Hi David, On 30-Apr-09, at 6:59 PM, David Greene wrote: > This is not scalable. > > So what I've done is a little experiment to see if I can unify all > SSE and AVX > SIMD instructions under one framework. I'll leave MMX and 3dNow > alone since > they're oddballs and hardly anyone uses them. I don't want to unnecessarily expand your scope, but while

Hello everyone, I wanted to let everybody know that I am going to enable the support for vector-select by default later today. Details: Currently the LLVM code-generator only supports 'select' [1] instructions with a boolean condition. Vectorizing compilers, such as the Intel OpenCL Vectorizer and the GCC vectorizer often use vector-select instructions to implements masks. This change

Here's the big RFC. A I've gone through and designed patterns for AVX, I quickly realized that the existing SSE pattern specification, while functional, is less than ideal in terms of maintenance. In particular, a number of nearly-identical patterns are specified all over for nearly-identical instructions. For example: let Constraints = "$src1 = $dst" in { multiclass