Hello Evan and Robert I have been investigating the unexpected test failures from the ARM nightly builders in order to get a better picture why the ARM backend don't pass the whole testsuite: I have run the failing tests manually on my arm board and can now categorize most of the thirteen unexpected CodeGen failures in four categories: 1. llvm don't lower MVT::i64 properly on arm errors http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/i64armLoweringRelatedErrors/ example: root at overo:/home/xerxes/llvm-test/fail/CodeGen/notnativelysupported# llvm-as < 2008-02-04-ExtractSubvector.ll | llc llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/include/llvm/Target/TargetLowering.h:158: llvm::TargetRegisterClass* llvm::TargetLowering::getRegClassFor(llvm::MVT) const: Assertion `RC && "This value type is not natively supported!"' failed. Stack dump: 0. Program arguments: llc 1. Running pass 'ARM Instruction Selection' on function '@main' Aborted 2. lowering sometimes produces unexpected results error http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/loweringproducesunexpectedresults/ example: root at overo:/home/xerxes/llvm-test/fail/CodeGen/loweringproducesunexpected# llvm-as < multiple-return-values-cross-block-with-invoke.ll | llc llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1579: llvm::SDValue<unnamed>::SelectionDAGLegalize::LegalizeOp(llvm::SDValue): Assertion `(Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == MVT::Flag)) && "Lowering call/formal_arguments produced unexpected # results!"' failed. Stack dump: 0. Program arguments: llc 1. Running pass 'ARM Instruction Selection' on function '@foo' Aborted 3. Could not match memory address errors http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/matchmemoryaddress_inlineasmfailure/ example: root at overo:/home/xerxes/llvm-test/fail/CodeGen/matchmemoryaddress# llvm-as < 2007-04-08-MultipleFrameIndices.ll | llc Could not match memory address. Inline asm failure! .file "<stdin>" Aborted 4. softfloat related errors http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/softenfloat_Do_not_know_how_to_soften_the_result_of_this_operator/ example: root at overo:/home/xerxes/llvm-test/fail/CodeGen/softenfloat# llvm-as < 2007-11-19-VectorSplitting.ll | llc SoftenFloatResult #0: 0x614e00: f32 = undef llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:54: void llvm::DAGTypeLegalizer::SoftenFloatResult(llvm::SDNode*, unsigned int): Assertion `0 && "Do not know how to soften the result of this operator!"' failed. Stack dump: 0. Program arguments: llc 1. Running pass 'ARM Instruction Selection' on function '@execute_shader' Aborted All of these errors can ofcourse be experienced on other architectures as well when generating .S files for arm using llc -march=arm There was some tests failing for the ExecutionEngine yet i am uncertain if it is a error since i it fails on X86 as well like this one: http://labb.zafena.se/shark-testing/llvmExecutionEngine200904/segfault/ example: root at overo:/home/xerxes/llvm-test/fail/ExecutionEngine200904/segfault# llvm-as < 2003-05-07-ArgumentTest.ll | lli - test Tried to execute an unknown external function: i32 (i8*)* puts Stack dump: 0. Program arguments: lli - test Aborted The unexpected tests that i have been investigation where those produced by the cfarm-arm nightly tester on 090321. I have uploaded a pdf of the testresult for future reference: http://labb.zafena.se/shark-testing/llvmTestLogs/arm090321.pdf Cheers and have a great day! Xerxes Evan Cheng skrev:> LLVM ARM v6 backend is in fairly good shape. Even the JIT passes > nearly the entire llvm test suite. There are some known missing bits: > > 1. Exception handling > 2. Atomic > > Not sure: > 3. Debugging support (should be trivial to hook up if it's not done) > > Also the thumb backend is not awesome. Its performance is not great. > > Evan > > On Apr 1, 2009, at 6:34 AM, Robert Schuster wrote: > > >> Hi, >> the ARM backend lacks some stuff like support for atomic intrinsics. I >> learned the hard way (crash). Lately I was told that the ARM backend >> of >> LLVM is generally in its early stages of development. >> >> I would like to know more about this. Which stuff is missing, known to >> be unstable and the like. >> >> Thanks in advance for taking the time. >> >> Regards >> Robert >> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >
Hi Xerxes,> 4. softfloat related errors > http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/softenfloat_Do_not_know_how_to_soften_the_result_of_this_operator/ > example: > > root at overo:/home/xerxes/llvm-test/fail/CodeGen/softenfloat# llvm-as < 2007-11-19-VectorSplitting.ll | llc > SoftenFloatResult #0: 0x614e00: f32 = undef > llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:54: void llvm::DAGTypeLegalizer::SoftenFloatResult(llvm::SDNode*, unsigned int): Assertion `0 && "Do not know how to soften the result of this operator!"' failed. > Stack dump: > 0. Program arguments: llc > 1. Running pass 'ARM Instruction Selection' on function '@execute_shader' > Abortedthis is now fixed. Ciao, Duncan.
Duncan Sands skrev:> Hi Xerxes, > > >> 4. softfloat related errors >> http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/softenfloat_Do_not_know_how_to_soften_the_result_of_this_operator/ >> example: >> >> root at overo:/home/xerxes/llvm-test/fail/CodeGen/softenfloat# llvm-as < 2007-11-19-VectorSplitting.ll | llc >> SoftenFloatResult #0: 0x614e00: f32 = undef >> llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:54: void llvm::DAGTypeLegalizer::SoftenFloatResult(llvm::SDNode*, unsigned int): Assertion `0 && "Do not know how to soften the result of this operator!"' failed. >> Stack dump: >> 0. Program arguments: llc >> 1. Running pass 'ARM Instruction Selection' on function '@execute_shader' >> Aborted >> > > this is now fixed. > > Ciao, > > Duncan. >Great work Duncan! I recompiled llvm and restested the failing softenfloat tests on my machine: 2007-11-19-VectorSplitting.ll OK! vector-constantexpr.ll OK! vector-constantexpr.ll OK! llvm-as < print-arith-fp.l l | llc SoftenFloatResult #0: 0x61aad8: f64 = frem 0x619fb0, 0x619ea0 llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r1/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:54: void llvm::DAGTypeLegalizer::SoftenFloatResult(llvm::SDNode*, unsigned int): Assertion `0 && "Do not know how to soften the result of this operator!"' failed. Stack dump: 0. Program arguments: llc 1. Running pass 'ARM Instruction Selection' on function '@main' Aborted uname -a Linux overo 2.6.28-omap1 #1 Mon Mar 2 08:40:39 PST 2009 armv7l unknown llc --version Low Level Virtual Machine (http://llvm.org/): llvm version 2.6svn Optimized build with assertions. Built Apr 8 2009(16:04:09). it seems we need to fix softenfloat f64 as well. Cheers Xerxes
On Apr 8, 2009, at 5:44 AM, Xerxes Rånby wrote:> Hello Evan and Robert > I have been investigating the unexpected test failures from the ARM > nightly builders in order to get a better picture why the ARM backend > don't pass the whole testsuite: I have run the failing tests > manually on > my arm board and can now categorize most of the thirteen unexpected > CodeGen failures in four categories:Thanks for investigating these failures! It is very helpful. (Thanks also to Duncan for fixing some of the problems so quickly.) I'll try to take a look at the remaining issues sometime soon.
Den 2009-04-08 14:44, Xerxes Rånby skrev:> Hello Evan and Robert > I have been investigating the unexpected test failures from the ARM > nightly builders in order to get a better picture why the ARM backend > don't pass the whole testsuite: I have run the failing tests manually on > my arm board and can now categorize most of the thirteen unexpected > CodeGen failures in four categories: > > 1. llvm don't lower MVT::i64 properly on arm errors > http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/i64armLoweringRelatedErrors/ > example: > > root at overo:/home/xerxes/llvm-test/fail/CodeGen/notnativelysupported# llvm-as< 2008-02-04-ExtractSubvector.ll | llc > llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/include/llvm/Target/TargetLowering.h:158: llvm::TargetRegisterClass* llvm::TargetLowering::getRegClassFor(llvm::MVT) const: Assertion `RC&& "This value type is not natively supported!"' failed. > Stack dump: > 0. Program arguments: llc > 1. Running pass 'ARM Instruction Selection' on function '@main' > Aborted > >Three of these i64 related test passes after applying the attached patch from pr 3898 ! http://llvm.org/bugs/show_bug.cgi?id=3898 Thanks Jakob! Could someone commit this one to the svn tree? [xranby at pusspuss llvm]$ llvm-as < test/CodeGen/Generic/2008-02-04-ExtractSubvector.ll | llc -march=arm .file "<stdin>" .text .globl main .align 2 main: mov r3, #0 .LBB1_1: @ bb15 b .LBB1_1 @ bb15 .size main, .-main [xranby at pusspuss llvm]$ llvm-as < test/CodeGen/X86/dagcombine-buildvector.ll | llc -march=arm .file "<stdin>" .text .globl test .align 2 test: ldr r1, [sp, #+12] str r1, [r0, #+12] ldr r1, [sp, #+8] str r1, [r0, #+8] stmia r0, {r2, r3} bx lr .size test, .-test [xranby at pusspuss llvm]$ llvm-as < test/CodeGen/Generic/select-cc.ll | llc -march=arm .file "<stdin>" .text .globl vector_select .align 2 vector_select: stmfd sp!, {r4, r5, r6, r7, lr} mov r4, r3 mov r5, r2 mov r6, r1 mov r7, r0 mov r2, #0 mov r3, #0 bl __gedf2 ldr r2, [sp, #+32] cmp r0, #0 mov r3, r4 movge r3, r2 ldr r1, [sp, #+28] cmp r0, #0 mov r2, r5 movge r2, r1 ldr r12, [sp, #+24] cmp r0, #0 mov r1, r6 movge r1, r12 ldr r12, [sp, #+20] cmp r0, #0 mov r0, r7 movge r0, r12 ldmfd sp!, {r4, r5, r6, r7, pc} .size vector_select, .-vector_select [xranby at pusspuss llvm]$ /* The failing i64 related tests are now only two left: */ (wrongcodegen) llvm-as < test/CodeGen/Generic/asm-large-immediate.ll | llc -march=arm | grep 68719476738 and (shifttolower) llvm-as < test/CodeGen/X86/vshift_split.ll | llc -march=arm llc: ARMISelLowering.cpp:1426: llvm::SDValue ExpandSRx(llvm::SDNode*, llvm::SelectionDAG&, const llvm::ARMSubtarget*): Assertion `N->getValueType(0) == MVT::i64 && (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && "Unknown shift to lower!"' failed. 0 llc 0x089afeb8 Stack dump: 0. Program arguments: llc -march=arm 1. Running pass 'ARM Instruction Selection' on function '@update' Avbruten (SIGABRT) [xranby at pusspuss llvm]$> 2. lowering sometimes produces unexpected results error > http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/loweringproducesunexpectedresults/ > example: > > root at overo:/home/xerxes/llvm-test/fail/CodeGen/loweringproducesunexpected# llvm-as< multiple-return-values-cross-block-with-invoke.ll | llc > llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1579: llvm::SDValue<unnamed>::SelectionDAGLegalize::LegalizeOp(llvm::SDValue): Assertion `(Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1&& Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == MVT::Flag))&& "Lowering call/formal_arguments produced unexpected # results!"' failed. > Stack dump: > 0. Program arguments: llc > 1. Running pass 'ARM Instruction Selection' on function '@foo' > Aborted > >This have been fixed by applying the patch made by Sandeep http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-April/021754.html Could someone commit this one to the svn tree?> 3. Could not match memory address errors > http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/matchmemoryaddress_inlineasmfailure/ > example: > > root at overo:/home/xerxes/llvm-test/fail/CodeGen/matchmemoryaddress# llvm-as< 2007-04-08-MultipleFrameIndices.ll | llc > Could not match memory address. Inline asm failure! > .file "<stdin>" > Aborted > >This one still needs a fix... :/> 4. softfloat related errors > http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/softenfloat_Do_not_know_how_to_soften_the_result_of_this_operator/ > example: > > root at overo:/home/xerxes/llvm-test/fail/CodeGen/softenfloat# llvm-as< 2007-11-19-VectorSplitting.ll | llc > SoftenFloatResult #0: 0x614e00: f32 = undef > llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:54: void llvm::DAGTypeLegalizer::SoftenFloatResult(llvm::SDNode*, unsigned int): Assertion `0&& "Do not know how to soften the result of this operator!"' failed. > Stack dump: > 0. Program arguments: llc > 1. Running pass 'ARM Instruction Selection' on function '@execute_shader' > Aborted > >This one are fixed and comitted to the svn tree! Thanks Duncan Cheers and have a great day! Xerxes