search for: softenfloatresult

...loat related errors > http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/softenfloat_Do_not_know_how_to_soften_the_result_of_this_operator/ > example: > > root at overo:/home/xerxes/llvm-test/fail/CodeGen/softenfloat# llvm-as < 2007-11-19-VectorSplitting.ll | llc > SoftenFloatResult #0: 0x614e00: f32 = undef > llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:54: void llvm::DAGTypeLegalizer::SoftenFloatResult(llvm::SDNode*, unsigned int): Assertion `0 && "Do not know...

...>> http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/softenfloat_Do_not_know_how_to_soften_the_result_of_this_operator/ >> example: >> >> root at overo:/home/xerxes/llvm-test/fail/CodeGen/softenfloat# llvm-as < 2007-11-19-VectorSplitting.ll | llc >> SoftenFloatResult #0: 0x614e00: f32 = undef >> llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:54: void llvm::DAGTypeLegalizer::SoftenFloatResult(llvm::SDNode*, unsigned int): Assertion `0 && "Do not k...

..." Aborted 4. softfloat related errors http://labb.zafena.se/shark-testing/llvmARMCodeGenFailures200904/softenfloat_Do_not_know_how_to_soften_the_result_of_this_operator/ example: root at overo:/home/xerxes/llvm-test/fail/CodeGen/softenfloat# llvm-as < 2007-11-19-VectorSplitting.ll | llc SoftenFloatResult #0: 0x614e00: f32 = undef llc: /usr/src/openembedded/overo/tmp/work/armv7a-angstrom-linux-gnueabi/llvm2.6-2.6-r0/llvm-2.6/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:54: void llvm::DAGTypeLegalizer::SoftenFloatResult(llvm::SDNode*, unsigned int): Assertion `0 && "Do not know how t...

...objections. Hi Thomas, With ISD::FMINNAN and ISD::FMAXNAN now easy to produce for any target due to these newly exposed intrinsics, I think these nodes should be handled in at least SelectionDAGLegalize::ExpandNode (for when the float type is legal but the operation is not) and DAGTypeLegalizer::SoftenFloatResult (for when the float type is not legal). Best, Alex

LLVM ARM v6 backend is in fairly good shape. Even the JIT passes nearly the entire llvm test suite. There are some known missing bits: 1. Exception handling 2. Atomic Not sure: 3. Debugging support (should be trivial to hook up if it's not done) Also the thumb backend is not awesome. Its performance is not great. Evan On Apr 1, 2009, at 6:34 AM, Robert Schuster wrote: > Hi, > the

Hi, the ARM backend lacks some stuff like support for atomic intrinsics. I learned the hard way (crash). Lately I was told that the ARM backend of LLVM is generally in its early stages of development. I would like to know more about this. Which stuff is missing, known to be unstable and the like. Thanks in advance for taking the time. Regards Robert -------------- next part -------------- A

...FMINNAN and ISD::FMAXNAN now easy to produce for any target >> due to these newly exposed intrinsics, I think these nodes should be >> handled in at least SelectionDAGLegalize::ExpandNode (for when the >> float type is legal but the operation is not) and >> DAGTypeLegalizer::SoftenFloatResult (for when the float type is not >> legal). >> >> Best, >> >> Alex >> > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20181107/a3bc8898/attachment.html>