search for: dsttype

...Greene wrote: > For example, I want to be able to do this: > > defm MOVH : > vs1x_fps_binary_vv_node_rmonly< > 0x16, "movh", undef, 0, > // rr > [(undef)], > // rm > [(set DSTREGCLASS:$dst, > (DSTTYPE (movlhps SRCREGCLASS:$src1, > (DSTTYPE (bitconvert > (v2f64 (scalar_to_vector > (loadf64 addr:$src2))))))))], > // rr Pat > [], >...

...one write a set of Pat<> patterns in a generic way? For example, I want to be able to do this: defm MOVH : vs1x_fps_binary_vv_node_rmonly< 0x16, "movh", undef, 0, // rr [(undef)], // rm [(set DSTREGCLASS:$dst, (DSTTYPE (movlhps SRCREGCLASS:$src1, (DSTTYPE (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))))], // rr Pat [], // rm Pat...

The TableGen language seems to be growing Lisp macros from two different directions. Che-Liang Chiou added a preprocessor with for loops, and David Greene added multidefs. It seems that some kind of macro facility is needed, perhaps we should discuss what it is supposed to look like? /jakob

...want to be able to do this: >> >> defm MOVH : >> vs1x_fps_binary_vv_node_rmonly< >> 0x16, "movh", undef, 0, >> // rr >> [(undef)], >> // rm >> [(set DSTREGCLASS:$dst, >> (DSTTYPE (movlhps SRCREGCLASS:$src1, >> (DSTTYPE (bitconvert >> (v2f64 (scalar_to_vector >> (loadf64 addr:$src2))))))))], >> // rr Pat >>...

...< 0x2D, "cvtsi2ss", sint_to_fp, "cvtsi2ss", "f32", "i32">; [Meanwhile, down in the guts...] class fp_cvt_scalar_VXSnrr< // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr bits<8> opc, string OpcodeStr, SDNode OpNode, string DstType, string SrcType, int CustomPatterns = 0, list<dag> patterns = [], string asm = "" >: fp_unary_vxs_n_rm_rr< opc, !cast<RegisterClass>(!patsubst("^f([0-9]+)","FR$1",!patsubst("^i([0-9]+)","GR$1",DstType))), [...] Bas...

...Node* storeOp = dyn_cast<StoreSDNode>(Op.Val); const SDValue& dstPtr = storeOp->getBasePtr(); const SrcValueSDNode* svdstVal = cast<SrcValueSDNode>(dstPtr.Val); const Value* dstVal = svdstVal->getValue(); int addressSpace = ADDRESS_NONE; const Type* dstType = dstVal->getType(); if (isa<PointerType>(dstType)) { const PointerType* ptrType = cast<PointerType>(dstType); addressSpace = ptrType->getAddressSpace(); } printf("Addr: %d\n", addressSpace); SDValue Res; .... return Res; } A...

...nt_to_fp, "cvtsi2ss", "f32", "i32">; > > [Meanwhile, down in the guts...] > > class fp_cvt_scalar_VXSnrr< > // Parent: avx_fp_cvt_scalar_xs_node_rm_DEF_V#NAME#_128rr > bits<8> opc, > string OpcodeStr, > SDNode OpNode, > string DstType, > string SrcType, > int CustomPatterns = 0, > list<dag> patterns = [], > string asm = "" >> : fp_unary_vxs_n_rm_rr< > opc, > !cast<RegisterClass>(!patsubst("^f([0-9]+)","FR$1",! > patsubst("^i([0-9]+)",&qu...

...STRegs, i16, i16, i16, simm16, immZExt16x>; >> >> multiclass ABD_NonCommutative<string asmstr, SDPatternOperator OpNode, >> RegisterClass srcAReg, RegisterClass srcBReg, >> RegisterClass dstReg, ValueType srcAType, ValueType >> srcBType, ValueType dstType, >> Operand ImmOd, ImmLeaf imm_type> >> { >> .... >> def IMM_MEM_MEM : SetABDIn<asmstr, ImmOd, memhx, memhx, >> [(directStore (dstType (OpNode >> imm_type:$srcA, (srcBType (load addr16:$srcB)))),...

...gt;>> >>> defm MOVH : >>> vs1x_fps_binary_vv_node_rmonly< >>> 0x16, "movh", undef, 0, >>> // rr >>> [(undef)], >>> // rm >>> [(set DSTREGCLASS:$dst, >>> (DSTTYPE (movlhps SRCREGCLASS:$src1, >>> (DSTTYPE (bitconvert >>> (v2f64 (scalar_to_vector >>> (loadf64 addr:$src2))))))))], >>> // rr P...

The address qualifier is stored in the type of %result. From that operand, you can get the Value and then call getType. The type for result should be a PointerType which you cast to a PointerType and get the getAddressSpace e.g. cast<PointerType>(Ty)->getAddressSpace() -- Mon Ping On Sep 17, 2008, at 1:06 PM, Villmow, Micah wrote: > How do I access the address qualifier

...b16u", unsignedSub, LOADRegs, GPRRegs, DSTRegs, i16, i16, i16, simm16, immZExt16x>; multiclass ABD_NonCommutative<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass srcBReg, RegisterClass dstReg, ValueType srcAType, ValueType srcBType, ValueType dstType, Operand ImmOd, ImmLeaf imm_type> { .... def IMM_MEM_MEM : SetABDIn<asmstr, ImmOd, memhx, memhx, [(directStore (dstType (OpNode imm_type:$srcA, (srcBType (load addr16:$srcB)))), addr16:$dstD)]>; ..... } class SetABDIn<s...

How do I access the address qualifier from the store instruction. Given the following code: define void @test_unary_op_anegate(float %x, float addrspace(11)* %result) nounwind { entry: %neg = sub float -0.000000e+000, %x ; <float> [#uses=1] store float %neg, float addrspace(11)* %result ret void } When I attempt to generate this code, I'm

...r generated by TableGen: llvm/lib/Target/X86/X86GenDAGISel.inc:91821: error: duplicate case value llvm/lib/Target/X86/X86GenDAGISel.inc:91442: error: previously used here This seems to happen because of a pattern I added for VEXTRACTF128 which uses extract_subreg: [(set DSTREGCLASS:$dst, (DSTTYPE (extract_subreg (vector_shuffle (SRCTYPE undef), (SRCTYPE SRCREGCLASS:$src1), VEXTRACTF128_shuffle_mask:$src2), x86_subreg_128bit)))], def x86_subreg_128bit : PatLeaf<(i32 1)>; Curiously, I...

...way? > > For example, I want to be able to do this: > > defm MOVH : > vs1x_fps_binary_vv_node_rmonly< > 0x16, "movh", undef, 0, > // rr > [(undef)], > // rm > [(set DSTREGCLASS:$dst, > (DSTTYPE (movlhps SRCREGCLASS:$src1, > (DSTTYPE (bitconvert > (v2f64 (scalar_to_vector > (loadf64 addr:$src2))))))))], > // rr Pat > [], &...

Here is the instruction in question: multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass dstReg, ValueType srcAType, ValueType dstType, Operand ImmOd, ImmLeaf imm_type> { def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, [(set dstReg:$dstD, (OpNode srcAReg:$srcA))]>; def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg, [(set dstReg:$dstD, (OpNode imm_type...

On Jun 9, 2009, at 12:39 PM, David Greene wrote: > On Tuesday 09 June 2009 14:34, Dan Gohman wrote: >> Can you describe what problem you're trying to solve here? Does it >> really need Regular Expressions? > > Yes. I want TableGen to be able to infer lots of stuff > programmatically. > This helps tremendously when specifying things like, oh, AVX. :) I

...5, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the instruction in question: > > multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass > srcAReg, > RegisterClass dstReg, ValueType srcAType, > ValueType dstType, Operand ImmOd, ImmLeaf imm_type> > { > def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, > [(set dstReg:$dstD, (OpNode > srcAReg:$srcA))]>; > def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg, > [(set...

On Tuesday 09 June 2009 14:34, Dan Gohman wrote: > Can you describe what problem you're trying to solve here? Does it > really need Regular Expressions? Yes. I want TableGen to be able to infer lots of stuff programmatically. This helps tremendously when specifying things like, oh, AVX. :) We could invent our own pattern matching syntax, but why?

...aylor <ryta1203 at gmail.com> wrote: >> >> Here is the instruction in question: >> >> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >> srcAReg, >> RegisterClass dstReg, ValueType srcAType, >> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >> { >> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >> [(set dstReg:$dstD, (OpNode >> srcAReg:$srcA))]>; >> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg, >>...

...com> wrote: >>> >>> Here is the instruction in question: >>> >>> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >>> srcAReg, >>> RegisterClass dstReg, ValueType srcAType, >>> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >>> { >>> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >>> [(set dstReg:$dstD, (OpNode >>> srcAReg:$srcA))]>; >>> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg, &...