search for: lowerstor

...ntPoolSDNode is what I want and when I try to cast the getBasePtr().Val of the StoreSDNode to a SrcValueSDNode it asserts on: Assertion failed: isa<X>(Val) && "cast<Ty>() argument of incompatible type!" This is what I'm attempting: SDValue LangTargetLowering::LowerSTORE(SDValue Op, SelectionDAG& DAG){ const StoreSDNode* storeOp = dyn_cast<StoreSDNode>(Op.Val); const SDValue& dstPtr = storeOp->getBasePtr(); const SrcValueSDNode* svdstVal = cast<SrcValueSDNode>(dstPtr.Val); const Value* dstVal = svdstVal->getValue();...

...s=1] store float %neg, float addrspace(11)* %result ret void } When I attempt to generate this code, I'm aborting on. Cannot yet select: 017E8230: ch = store 017E7DF0, 017E8098, 017E8010, 017E81A8 <0035A078:0> alignment=4 So I am doing a custom Store function. In my LowerStore function, I get an SDValue w/ opcode of 119(store) and 4 child Operands Operand 0 is the entry token which I assume I can ignore Operand 1 is the source data(%neg), which I finally can handle correctly thanks to Eli Operand 2 is the dst location with two children, an EntryToken and Register(%re...

...allowsUnalignedMemoryOperations() always returns 'false', and the setOperationAction()s for i8,i16,i32 loads and stores are all 'Custom'. I'm running into a problem where DAGCombiner is being too clever for me; it runs LegalizeDAG, which calls my custom LowerLOAD() and LowerSTORE() routines (which emit between 1 and O(10) SDValues, depending on alignment information), and then runs DAGCombine. To lower an i16 STORE that is known to be in the high-addressed 2 bytes of a word on my little-endian target, I emit and LD4 from the word-aligned address and an SRL 16 to shift...

...neg, float addrspace(11)* %result > ret void > } > When I attempt to generate this code, I’m aborting on. > Cannot yet select: 017E8230: ch = store 017E7DF0, 017E8098, > 017E8010, 017E81A8 <0035A078:0> alignment=4 > So I am doing a custom Store function. > In my LowerStore function, I get an SDValue w/ opcode of 119(store) > and 4 child Operands > Operand 0 is the entry token which I assume I can ignore > Operand 1 is the source data(%neg), which I finally can handle > correctly thanks to Eli > Operand 2 is the dst location with two children, an E...

Hi all, All of the data types are 32 bits and the pointer is 32 bit. Therefore, I need word adressing instead of byte adressing to use 8 GB memory. I was told that R600 uses word adressing and I looked at its codes but I could not find where the backends handles word adressing. Do you have any ideas about it? Thanks in advance. -------------- next part -------------- An HTML attachment was

On Thu, 6 Sep 2018 at 20:01, Tim Northover <t.p.northover at gmail.com> wrote: > I just did a very quick experiment where I made lowerFP_TO_SINT and > lowerFP_TO_SINT_STORE return SDValue() (which is the marker for "I > don't want to handle this"). I just tried this, but the compiler still crashes with the same error. Maybe our experiments were different. To make

Hi All, Some targets don't provide subword (e.g., i8 and i16 for a 32-bit machine) load and store instructions, so currently we have to custom-lower Load- and StoreSDNodes in our backends. For examples, see LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp. I believe it's possible to support this lowering in a target-agnostic fashion in LegalizeDAG.cpp, similar to what is done for non-naturally-aligned loads and stores using the allowsUnalignedMemoryAccesses() target hook. I wanted to see if there...

...ryOperations() always returns 'false', and the > setOperationAction()s for i8,i16,i32 loads and stores are all 'Custom'. > >     I'm running into a problem where DAGCombiner is being too clever > for me; it runs LegalizeDAG, which calls my custom LowerLOAD() and > LowerSTORE() routines (which emit between 1 and O(10) SDValues, > depending on alignment information), and then runs DAGCombine.  To lower > an i16 STORE that is known to be in the high-addressed 2 bytes of a word > on my little-endian target, I emit and LD4 from the word-aligned address > and an...

...returns 'false', and the >> setOperationAction()s for i8,i16,i32 loads and stores are all 'Custom'. >> >> I'm running into a problem where DAGCombiner is being too clever >> for me; it runs LegalizeDAG, which calls my custom LowerLOAD() and >> LowerSTORE() routines (which emit between 1 and O(10) SDValues, >> depending on alignment information), and then runs DAGCombine. To lower >> an i16 STORE that is known to be in the high-addressed 2 bytes of a word >> on my little-endian target, I emit and LD4 from the word-aligned address...

...ul 2011, at 03:34, Matt Johnson wrote: > Hi All, > Some targets don't provide subword (e.g., i8 and i16 for a 32-bit > machine) load and store instructions, so currently we have to > custom-lower Load- and StoreSDNodes in our backends. For examples, see > LowerLOAD() and LowerSTORE() in {XCore,CellSPU}ISelLowering.cpp. I > believe it's possible to support this lowering in a target-agnostic > fashion in LegalizeDAG.cpp, similar to what is done for > non-naturally-aligned loads and stores using the > allowsUnalignedMemoryAccesses() target hook. The XCore...

...', and the >>> setOperationAction()s for i8,i16,i32 loads and stores are all 'Custom'. >>> >>>     I'm running into a problem where DAGCombiner is being too clever >>> for me; it runs LegalizeDAG, which calls my custom LowerLOAD() and >>> LowerSTORE() routines (which emit between 1 and O(10) SDValues, >>> depending on alignment information), and then runs DAGCombine.  To lower >>> an i16 STORE that is known to be in the high-addressed 2 bytes of a word >>> on my little-endian target, I emit and LD4 from the word-ali...