We know. Someone offered to do the Intel version, but did little more than a huge cut and paste of the AT&T version and then lost interest. No one else has had the time or inclination to finish the (barely begun) job. Patches accepted :) Ralph Corderoy wrote:> Hi, > > >> It's a long way towards it: >> >> # AT&T. # Intel. >> .text .text >> .align 16 .align 16 >> .globl main .globl main >> .type main, @function >> main: main: >> subl $12, %esp sub esp, 12 >> fnstcw 10(%esp) fnstcw word ptr [esp + 10] >> movb $2, 11(%esp) mov byte ptr [esp + 11], 2 >> fldcw 10(%esp) fldcw word ptr [esp + 10] >> movl 20(%esp), %eax mov eax, dword ptr [esp + 20] >> movl 4(%eax), %eax mov eax, dword ptr [eax + 4] >> > > Whoops. I've provided my post-processed version of lli's Intel output > which, since I removed the `%' and lowered the `DWORD PTR' isn't a good > example. Still, you get the gist; there are already significant > differences between the two. > > Cheers, > > > Ralph. > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > > >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20060429/f8fc076a/attachment.html>
Jeff,
I had a working MASM Writer backend but it never got committed. I still have the
code so could redo it relatively quickly.
Aaron
----- Original Message -----
From: Jeff Cohen
To: LLVM Developers Mailing List
Sent: Saturday, April 29, 2006 7:56 PM
Subject: Re: [LLVMdev] Intel vs. AT&T Assembly.
We know. Someone offered to do the Intel version, but did little more than a
huge cut and paste of the AT&T version and then lost interest. No one else
has had the time or inclination to finish the (barely begun) job. Patches
accepted :)
Ralph Corderoy wrote:
Hi,
It's a long way towards it:
# AT&T. # Intel.
.text .text
.align 16 .align 16
.globl main .globl main
.type main, @function
main: main:
subl $12, %esp sub esp, 12
fnstcw 10(%esp) fnstcw word ptr [esp + 10]
movb $2, 11(%esp) mov byte ptr [esp + 11], 2
fldcw 10(%esp) fldcw word ptr [esp + 10]
movl 20(%esp), %eax mov eax, dword ptr [esp + 20]
movl 4(%eax), %eax mov eax, dword ptr [eax + 4]
Whoops. I've provided my post-processed version of lli's Intel output
which, since I removed the `%' and lowered the `DWORD PTR' isn't a
good
example. Still, you get the gist; there are already significant
differences between the two.
Cheers,
Ralph.
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LLVM Developers mailing list
LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
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On Sat, 29 Apr 2006, Jeff Cohen wrote:> We know. Someone offered to do the Intel version, but did little more than a > huge cut and paste of the AT&T version and then lost interest. No one else > has had the time or inclination to finish the (barely begun) job. Patches > accepted :)Actually, that's not true. The LLVM X86 backend started out emitting intel mode for use with GAS and it's "intel syntax mode" (which does use registers with %'s). Unfortunately GAS has (or commonly available versions have) a number of bugs in intel syntax mode (e.g. you can't define a function named 'dword'), so we switched to using AT&T syntax. Intel syntax mode was retained because it's nicer to read :), and because it may be useful in the future. As Jeff says, patches are welcome to make it do something useful, e.g. be assemblable with MASM or NASM. -Chris> Ralph Corderoy wrote: >> Hi, >> >> >>> It's a long way towards it: >>> >>> # AT&T. # Intel. >>> .text .text >>> .align 16 .align 16 >>> .globl main .globl main >>> .type main, @function >>> main: main: >>> subl $12, %esp sub esp, 12 >>> fnstcw 10(%esp) fnstcw word ptr [esp + 10] >>> movb $2, 11(%esp) mov byte ptr [esp + 11], 2 >>> fldcw 10(%esp) fldcw word ptr [esp + 10] >>> movl 20(%esp), %eax mov eax, dword ptr [esp + 20] >>> movl 4(%eax), %eax mov eax, dword ptr [eax + 4] >>> >> >> Whoops. I've provided my post-processed version of lli's Intel output >> which, since I removed the `%' and lowered the `DWORD PTR' isn't a good >> example. Still, you get the gist; there are already significant >> differences between the two. >> >> Cheers, >> >> >> Ralph. >> >> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> >> >> >>-Chris -- http://nondot.org/sabre/ http://llvm.org/
On Sun, 30 Apr 2006, Jeff Cohen wrote: Jeff, many appologies. I slightly misread what you wrote, and came across more strongly that was appropriate: I'm sorry! :( :(> Let's see. Ralph correctly points out that LLVM isn't producing anything > like Intel syntax. ...This is not true. LLVM produces something very close to what GAS accepts in intel mode: that is, we produce fully intel syntax (e.g. "DWORD PTR", no opcode size suffixes, etc) but we prepend % onto registers. This is what GAS expects (i.e., it's gas intel mode). I believe there is a GAS option to turn off the % prefix, but we never used it because it had other bugs.> No, %reg is not Intel syntax, no matter what gas thinks.There are several dialects of "intel mode", and GAS's is just one. Greater variation is due to differences in pseudo ops.> Last June, Aaron Gray offered to fix Intel mode so that it actually produced > Intel syntax. He offered was a gigantic cut and paste: > http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20050627/026872.html. > Then he apparently lost interest, though he now claims he had finished it > after all but simply neglected to give us a patch.Yup, that's true. Note, however, that that patch just moved around existing functionality, it didn't change or add anything (hence the use of the term "refactor"). Specifically, when I said "Actually, that's not true.", what I meant is that this: "Someone offered to do the Intel version, but did little more than a huge cut and paste of the AT&T version and then lost interest." ... is not true. The current Intel version is based on our original support for GAS Intel mode, it is not based on AT&T syntax support at all (which, again, came after gas intel syntax support). As was independently pointed out, we're quite close to supporting MASM (or whatever) intel syntax. Removing the %'s, for example, is trivial. Anyone who wants to do so is welcome to. The current -x86-asm-syntax=intel support is not currently compatible with any assembler that I know of. Patches to make it useful are welcome. -Chris -- http://nondot.org/sabre/ http://llvm.org/
Hi Chris,> The LLVM X86 backend started out emitting intel mode for use with GAS > and it's "intel syntax mode" (which does use registers with %'s). > Unfortunately GAS has (or commonly available versions have) a number > of bugs in intel syntax mode (e.g. you can't define a function named > 'dword'), so we switched to using AT&T syntax.Ah, OK. The current gas manual says Intel register operands are undelimeted, i.e. no `%'. Perhaps they've changed. http://www.gnu.org/software/binutils/manual/gas-2.9.1/html_chapter/as_16.html#IDX585> Intel syntax mode was retained because it's nicer to read :), and > because it may be useful in the future. As Jeff says, patches are > welcome to make it do something useful, e.g. be assemblable with MASM > or NASM.NASM might be the nicer target since it's GNU LGPL and runs on multiple OS. Its home page is broken at the moment, but the manual pages work. http://nasm.sourceforge.net/doc/html/nasmdoc0.html You went onto write:> > Let's see. Ralph correctly points out that LLVM isn't producing > > anything like Intel syntax. ..."Oh, no I didn't". :-) It was me that was saying llc's att and intel are already very different but both happen to have `%'.> This is not true. LLVM produces something very close to what GAS > accepts in intel mode: that is, we produce fully intel syntax (e.g. > "DWORD PTR", no opcode size suffixes, etc) but we prepend % onto > registers. This is what GAS expects (i.e., it's gas intel mode). I > believe there is a GAS option to turn off the % prefix, but we never > used it because it had other bugs.OK, looks like they may have made that the default now.> As was independently pointed out, we're quite close to supporting MASM > (or whatever) intel syntax. Removing the %'s, for example, is > trivial. Anyone who wants to do so is welcome to. The current > -x86-asm-syntax=intel support is not currently compatible with any > assembler that I know of. Patches to make it useful are welcome.OK. Thanks for clarifying. Cheers, Ralph.