Chris Lattner wrote:> On Tue, 8 Jun 2004, Vladimir Prus wrote: > > While adding support for branch instructions in my backend, I run into a > > trouble. The code to handle branches looks like: > > The machine code after instruction selection is: > > > > entry (0x8681458): > > %reg1024 = load <fi#-1> > > %reg1025 = load <fi#-2> > > setcc %reg1024, %reg1025 > > goto %disp(label then) > > goto %disp(label else) > > I assume that the two unconditional gotos are just test code, right? If > not, the second one is dead.Yes, in the final form there will be "iflt" instruction before the first goto, making it conditional.> > The code after "goto" is disturbing. It looks like spill code, but it's > > not going to be ever executed. Any ideas why it's generated? Is there any > > additional information I should provide? > > Yup, just add the "isTerminator" bit on your gotos in your tablegen > description for the instruction. This informs the code generator that any > spill code has to go above the instructions.Thanks, this works! I don't yet understand why spill code is needed there at all, but I'll return to that when I have branches working correctly. - Volodya
On Wed, 9 Jun 2004, Vladimir Prus wrote:> > I assume that the two unconditional gotos are just test code, right? If > > not, the second one is dead. > > Yes, in the final form there will be "iflt" instruction before the first goto, > making it conditional.Ah, ok :)> > > The code after "goto" is disturbing. It looks like spill code, but it's > > > not going to be ever executed. Any ideas why it's generated? Is there any > > > additional information I should provide? > > > > Yup, just add the "isTerminator" bit on your gotos in your tablegen > > description for the instruction. This informs the code generator that any > > spill code has to go above the instructions. > > Thanks, this works! I don't yet understand why spill code is needed there at > all, but I'll return to that when I have branches working correctly.I'm not sure either. Can you send the code before and after register allocation? You might also try -regalloc=linearscan, as the default allocator is, uhhh, non-optimal. -Chris -- http://llvm.cs.uiuc.edu/ http://www.nondot.org/~sabre/Projects/
Chris Lattner wrote:> > Thanks, this works! I don't yet understand why spill code is needed there > > at all, but I'll return to that when I have branches working correctly. > > I'm not sure either. Can you send the code before and after register > allocation?Attached.> You might also try -regalloc=linearscan, as the default > allocator is, uhhh, non-optimal.Ehm.... I get this: llc: LiveIntervals.cpp:166: virtual bool llvm::LiveIntervals::runOnMachineFunction(llvm::MachineFunction&): Assertion `r2iit != r2iMap_.end()' failed. - Volodya -------------- next part -------------- Code after instruction selection # Machine code for _Z3addii(): <fi #-2> is 4 bytes fixed at location [SP-20] <fi #-1> is 4 bytes fixed at location [SP-16] entry (0x8681458): %reg1024 = load <fi#-1> %reg1025 = load <fi#-2> setcc %reg1024, %reg1025 goto %disp(label then) goto %disp(label else) then (0x8681688): %reg1026 = + %reg1025, %reg1024 %gr7 = move %reg1026 return else (0x86815e0): %reg1027 = + %reg1025, %reg1024 %gr7 = move %reg1028 return # End machine code for _Z3addii(). Code after register allocation # Machine code for _Z3addii(): <fi #-2> is 4 bytes fixed at location [SP-20] <fi #-1> is 4 bytes fixed at location [SP-16] <fi #0> is 4 bytes <fi #1> is 4 bytes <fi #2> is 4 bytes entry (0x8681458): %gr0 = load <fi#-1> %gr1 = load <fi#-2> setcc %gr0, %gr1 store <fi#0>, %gr0 store <fi#1>, %gr1 goto %disp(label then) goto %disp(label else) then (0x8681688): %gr0 = load <fi#1> %gr1 = load <fi#0> %gr0 = + %gr0, %gr1 %gr7 = move %gr0 return else (0x86815e0): %gr0 = load <fi#1> %gr1 = load <fi#0> %gr0 = + %gr0, %gr1 %gr0 = load <fi#2> %gr7 = move %gr0 return # End machine code for _Z3addii().